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Abstract: Semiconductor nanowires (NWs) represent an ideal system for investigating low-
dimensional physics and are expected to play an important role as both interconnects and
functional device elements in nanoscale electronic and optoelectronic devices. Here we re-
view a series of key advances defining a new paradigm of bottom-up assembling integrated
nanosystems using semiconductor NW building blocks. We first introduce a general ap-
proach for the synthesis of a broad range of semiconductor NWs with precisely controlled
chemical composition, physical dimension, and electronic, optical properties using a metal
cluster-catalyzed vapor–liquid–solid growth mechanism. Subsequently, we describe rational
strategies for the hierarchical assembly of NW building blocks into functional devices and
complex architectures based on electric field or micro-fluidic flow. Next, we discuss a vari-
ety of new nanoscale electronic device concepts including crossed NW p-n diode and crossed
NW field effect transistors (FETs). Reproducible assembly of these scalable crossed NW de-
vice elements enables a catalog of integrated structures, including logic gates and computa-
tional circuits. Lastly, we describe a wide range of photonic and optoelectronic devices, in-
cluding nanoscale light-emitting diodes (nanoLEDs), multicolor LED arrays, integrated
nanoLED–nanoFET arrays, single nanowire waveguide, and single nanowire nanolaser. The
potential application of these nanoscale light sources for chemical and biological analyses is
discussed.
INTRODUCTION
The rapid miniaturization of electronics to the submicron scale has led to remarkable increases in com-
puting power, while at the same time enabling cost reductions [1,2]. However, as the microelectronic
industry advances toward ever smaller devices, it is believed that both physical and economic factors of
current top-down silicon technology will soon limit further advances [3]. To go beyond these limits and
fuel the expected demands of future society will require revolutionary breakthroughs rather than cur-
rent evolutionary progress. In general terms, bottom-up assembled nanoscale electronics could provide
*Pure Appl. Chem. 76, 2051–2099 (2004). A collection of invited, peer-reviewed articles by the winners of the 2004 IUPAC Prize
for Young Chemists.
‡Corresponding author
2051
2052 Y. HUANG AND C. M. LIEBER
unparalleled speed, storage, and size reductions and hold the promise of powering future electronic de-
vices that can outperform existing devices and open up totally new opportunities. To enable integrated
nanoelectronics will require conceptually new device building blocks, scalable circuit architectures, and
fundamentally different fabrication strategies. A bottom-up approach, where functional electronic struc-
tures are assembled from chemically synthesized, well-defined nanoscale building-blocks, has the po-
tential to go far beyond the limits of top-down technology by defining key nanometer-scale metrics
through chemical synthesis and subsequent assemblynot by lithography [4–7].
Previous studies have led to a broad range of proof-of-concept nanoscale devices including diodes
and transistors based on individual organic molecules [8–12], quantum dots [13,14], or carbon nano-
tubes (NTs) [15,16]. However, these studies of individual nanodevices represent only an initial step to-
ward nanoelectronic circuits. It remains a great challenge to advance from a single device level to the
functional circuit level due to (1) the insufficient control of the properties of individual building blocks,
(2) low device-to-device reproducibility, and (3) the lack of reliable methods for efficiently assembling
and integrating building blocks into device arrays and circuits. Therefore, to move to this critical level
of complexity and achieve integrated nanocircuits requires three fundamental advances, including (1)
the development of rational approaches for the synthesis of nanoscale building blocks with precisely
controlled chemical composition, physical dimension, and electronic, optical properties; (2) the devel-
opment of rational strategies for the assembly of building blocks into increasingly complex structures;
and (3) the demonstration of new nanodevice concepts that can be implemented in high yield by as-
sembly approaches, and the development of new circuit architectures that are amenable to integration
via self- or directed-assembly.
Central to the bottom-up approach are the nanoscale building blocks. One-dimensional (1D)
nanostructures represent the smallest dimension structure that can efficiently transport electrical carri-
ers, and thus are ideally suited to the critical and ubiquitous task of moving and routing charges, which
constitute information, in nanoelectronics. In addition, 1D nanostructures can also exhibit critical de-
vice function, and thus can be exploited as both the wiring and device elements in future architectures
for functional nanosystems. In this regard, two material classes, semiconductor nanowires (NWs) and
carbon NTs, have shown particular promise. Single-walled NTs have been used to fabricate field effect
transistors (FETs) [17,18], diodes [19,20], and logic circuits [21,22]. However, the inability to control
whether NT building blocks are semiconducting or metallic and difficulties in manipulating individual
NTs have made device fabrication largely a random event, and thus pose a significant barrier to achiev-
ing highly integrated nanocircuits.
Semiconductor NWs represent another important and highly versatile nanometer-scale wire struc-
tures [23,24]. In contrast to NTs, semiconductor NWs can be rationally and predictably synthesized in
single crystal form with all key parameters, including chemical composition, diameter, and length, and
doping/electronic properties, controlled [25–27]. Semiconductor NWs thus represent the best-defined
class of nanoscale building blocks, and this precise control over key variables has correspondingly en-
abled a wide range of devices and integration strategies to be pursued. For example, semiconductor
NWs have been assembled into a series of electronic electronics devices including crossed NW p-n
diodes [28–31], crossed NW-FETs [30], nanoscale logic gates and computation circuits [30], as well as
optoelectronic devices including nanoscale light-emitting diodes (LEDs) [31] and lasers [32]. In con-
trast to NTs, NW devices can be assembled in a rational and predictable manner because the size, in-
terfacial properties, and electronic properties of the NWs can be precisely controlled during synthesis,
and moreover, reliable methods exist for their parallel assembly [28,33]. In addition, it is possible to
combine distinct NW building blocks in ways not possible in conventional electronics and to leverage
the knowledge base that exists for the chemical modification of inorganic surfaces [34,35] to produce
semiconductor NW devices that achieve new function and correspondingly lead to unexpected device
and system concepts.
Here we review a series of key advances that defined a new paradigm of bottom-up assembly of
nanoscale electronics and optoelectronics from semiconductor NWs building blocks. We first introduce
a general approach for the synthesis of a broad range of semiconductor NW building blocks with con-
trolled properties. Next, we describe rational strategies for the hierarchical assembly of NWs into in-
creasingly complex architectures. Lastly, we will discuss a variety of nanoscale electronic and opto-
electronic devices and circuits assembled from these NW building blocks.
Fig. 1 Semiconductor NW building blocks. (a) Schematics illustrating the underlying concept for catalytic growth
of NWs. Liquid catalytic clusters act as the energetically favored site for localized chemical reaction, absorption of
vapor-phase reactant and crystallization of crystalline NWs. (b) The figure shows a scanning electron microscope
(SEM) image of as-synthesized semiconductor NWs. The circular insets show transmission electron microscope
(TEM) images of the NWs. (c) Table summarizing NW materials grown with metal cluster-mediated catalytic
approach. Adapted from [25].
The basic electronic properties of NWs can be characterized using electrical transport studies in
a nanowire field effect transistor (NW-FET) configuration (Figs. 2a,b). The NW-FETs are prepared by
dispersing a suspension of NWs in ethanol onto the surface of an oxidized silicon substrate, where the
underlying conducting silicon is used as a global back gate [27,28,42]. Source and drain electrodes are
defined by electron beam lithography followed by electron beam evaporation of metal contacts, and
electrical transport measurements are done at room temperature. Current (I) vs. source-drain voltage
(Vsd) and I vs. gate voltage (Vg) is then recorded for an NW-FET to characterize its electrical proper-
ties. Gate sweeping measurement of the NW-FET enables elucidation of important qualitative and
quantitative properties of NWs. For example, changes in Vg produce variations in the electrostatic po-
tential of the NW, and hence modulate the carrier concentration and conductance of the NW (Fig. 2b).
Depending on the conductance modulation, it is possible to determine the doping type and estimate the
carrier mobility in individual NWs using standard transistor formula: dI/dVg = µ(C/L2)Vsd and
C ≅ 2πεε0L/ln(2h/r), where µ is the carrier mobility, C is the capacitance, ε is dielectric constant, h is
the thickness of the SiO2 dielectric, L is the length, and r is radius of the NW [42]. In this way, we have
characterized a broad range of NW materials including p-type Si, n-type GaN, CdS, and InP NWs. In
all cases, the NW materials show excellent carrier mobility comparable to bulk materials (Fig. 2c) [43],
which demonstrates the high quality of these materials.
Fig. 2 Nanowire electronic properties. (a) Schematic of an NW-FET used to characterize electrical transport
properties of individual NWs. (inset) SEM image of an NW-FET; two metal electrodes, which correspond to source
and drain, are visible at the left and right sides of the image. (b) Source-drain current vs. source-drain voltage for
an n-type InP NW-FET. The numbers inside the plot indicate the corresponding gate voltages (Vg). The inset shows
current vs. Vg for Vsd of 0.1 V. (c) Table summarizing carrier mobility in various NW materials in comparison with
their bulk material counterpart of similar carrier concentration.
We have also carried out optical studies to investigate the photoluminescence properties of these
NW materials [39,44]. Photoluminescence measurements were made on individual NWs using a home-
built microluminescence instrument. Studies on a broad range of compound semiconductor NWs in-
cluding GaN, CdS, CdSeS, and CdSe showed clean luminescence with spectra maxima of ~370, ~510,
~600, and ~700 nm, respectively [31], which are consistent with near band edge emission in these ma-
terials, and thus demonstrate excellent optical properties of these NW materials. Furthermore, photolu-
minescence studies on InP NWs of variable sizes showed systematic blue-shift of emission peak from
~900 to ~810 nm as the diameter of the InP NWs is reduced from 50 to 10 nm, which can be attributed
to quantum confinement effect [44]. Therefore, it is possible to control the emission wavelength of these
NW materials by either varying the chemical composition or physical dimension, thus offering the
greatest flexibility to precisely tune the color of nano-photonic devices.
Fig. 3 E-field-directed assembly of NWs. (a) Schematic view of E-field alignment. (b) Parallel array of NWs
aligned between two parallel electrodes. (c) Spatially positioned parallel array of NWs obtained following E-field
assembly. The top inset shows 15 pairs of parallel electrodes with individual NWs bridging each diametrically
opposed electrode pair. (d) Crossed NW junction obtained using layer-by-layer alignment with the E-field applied
in orthogonal directions in the two assembly steps. Adapted from [28].
individual NWs can be positioned to bridge pairs of diametrically opposed electrodes and form a par-
allel array. In addition, by changing the E-field direction with sequential NW solutions, the alignment
can be carried out in a layer-by-layer fashion to produce crossed NW junctions (Fig. 3d). These results
demonstrate clearly that E-field-directed assembly can be used to align and position individual NWs
into parallel and crossed arrays, which correspond to two basic geometries for integration, and thus pro-
vide one robust approach for rational and parallel assembly of nanoscale device arrays.
Fig. 4 Fluidic flow-directed assembly of NWs. (a,b) Schematic (a) and SEM image (b) of parallel NW arrays
obtained by passing a NW solution through a channel on a substrate; (c,d) Schematic (c) and SEM image (d) of
crossed NW matrix obtained by orthogonally changing the flow direction in a sequential flow alignment process.
(e,f) Schematic (e) and SEM image (f) of regular NW arrays obtained by flowing NW solution over a chemically
patterned surface. (g,h) Parallel and crossed NW device arrays obtained with fluidic flow assembly. Adapted from
[33].
bled at positions defined by the chemical pattern, and moreover, show that the periodic patterns can or-
ganize the NWs into regular superstructures. It is important to recognize that the patterned surface alone
does not provide good control of the 1D nanostructure organization. Assembly of NTs [48,49] and NWs
on patterned substrates shows that 1D nanostructures align with bridging and looping structures over
the patterned areas and show little directional control. Our use of fluidic flows avoids these significant
problems and enables controlled assembly in one or more directions. By combining this approach with
other surface patterning methods, such as phase separation in diblock copolymers [50] and spontaneous
ordering of molecules [51], it should be possible to generate well-ordered NW arrays without the lim-
itations of conventional lithography.
The above discussions clearly demonstrate that NWs can be assembled on the surface with con-
trolled orientation and spatial location. By combining them with conventional lithography approach, a
variety of integrated device structures including parallel arrays (Fig. 4g) [52] and crossed arrays
(Fig. 4h) [33] can be explored. Such integrated device arrays offers a variety of opportunities for us to
investigate the fundamental properties of these NW materials and explore them for various device ap-
plication. In particular, the crossed NW matrix represents an important geometrical configuration for
nanocircuits, where each crossing point can function as an independently addressable nanoscale device
element.
NANOWIRE ELECTRONICS
The ability to rationally synthesize NWs with controlled electronic properties and to assemble NWs into
regular arrays readily enabled us to explore these NW structures for a variety of functional device ar-
rays.
Fig. 5 Crossed nanowire devices. (a) Top, current-voltage (I-V) relation of the crossed p-n diode. Linear or nearly
linear I-V behavior of the p- (blue) and n-type (green) NWs indicates good contact between NWs and metal
electrodes. I-V curves across the junction (red) show clear current rectification. The top-left inset shows histogram
of turn-on voltage for over 70 as-assembled junctions showing a narrow distribution around 1 V. The bottom-right
inset shows a typical SEM image of a crossed NW p-n diode. Scale bar: 1 µm. (b) I-V behavior for a 4(p)x1(n)
multiple junction array. Inset shows an SEM image of a NW p-n diode array. (c) Schematics illustrating the crossed
NW-FET concept. (d) Gate-dependent I-V characteristics of a cNW-FET formed using a p-NW as the conducting
channel and n-NW as the local gate. The red and blue curves in the inset show Isd vs. Vgate for n-NW (red) and
global back (blue) gates when the Vsd is set at 1 V. The conductance modulation (>105) of the FET is much more
significant with the NW gate than that with a global back gate (<10). Adapted from [30].
Fig. 9 Nanowire optical waveguide, cavity, and laser with optical excitation. (a) Schematic showing an NW as an
optical waveguide; with cleaved ends it defines a Fabry–Perot cavity. (b) SEM image of a cleaved CdS NW end.
Scale bar, 100 nm. (c) Room-temperature photoluminescence image of a CdS NW uniformly excited with a
mercury lamp. (d) Photoluminescence spectrum from the NW end exhibiting periodic intensity modulation, which
corresponds to the Fabry–Perot modes of the NW. (e) Emission spectra from a CdS NW end with a pump power
of 190, 197, and 200 mW (red, blue, and green) recorded at 8 K show preferential gain at single mode and
demonstrate laser emission. Adapted from [32].
Fig. 10 Nanowire optical waveguide, cavity, and laser with electrical excitation. (a) Device schematic illustrating
a p-n diode formed between p-Si and n-CdS NWs, where the CdS NW forms the cavity and active medium. (b)
Optical image of a device with arrows highlighting the cross-point (blue) and CdS NW end (green). Scale bar, 5
µm. (c,d) The electroluminescence image obtained at room temperature with the device forward biased at 5 V.
White light illumination is used in image (c) to show the electrodes. The two bright spots highlighted by blue and
green arrows correspond to the emission from the cross-point and end, respectively. (e) Electroluminescence
spectra from the NW end show periodic intensity modulation, demonstrating NW can function as optical
waveguide and cavity in this injection device. (f) Schematic showing a hybrid device structure. In this structure,
electrons and holes can be injected into the CdS nanowire cavity along the whole length from the top metal layer
and the bottom p-Si layer, respectively. (g) Optical image of a device described in (f). The arrow highlights the
exposed CdS NW end. Scale bar, 5 µm. (h) Electroluminescence image recorded from this device at room-
temperature with an injection current of ca. 80 µA. The arrow highlights emission from the CdS NW end. The
dashed line highlights the NW position. (i) Emission spectra from a CdS nanowire device with injection currents
of 200 µA (red) and 280 µA (green) recorded at 8 K. These spectra are offset by 0.10 intensity units for clarity.
Adapted from [32].
For example, a two-input logic OR gate was realized using a 2(p) by 1(n) crossed NW p-n diode
array [30]. When either of the input to the p-NW is high, a high output is obtained at the n-NW as the
p-n diode is forward biased; a low output is only achieved when both inputs are low; and thus realizing
the same function as a conventional logic “OR” gate (Figs. 6a,b). A logic AND gate was also assem-
bled from two p-n diodes and one cNW-FET (Figs. 6c,d), and a logic NOR gate with gain over 5 was
assembled from three cNW-FETs in series (Figs. 6e,f). Importantly, logic OR, AND, and NOR gates
form a complete set of logic elements and enable the organization of virtually any logic circuits. For ex-
Fig. 6 Nanoscale logic gates. (a,b) Schematic and measured output vs. address level relation for a logic OR gate
assembled from two-crossed NW p-n diode. The insets in (a) show the SEM image and equivalent electronic circuit
of the device. The bar is 1 µm. The inset in (b) shows the experimental truth table for nano-OR gate. (c,d)
Schematic and measured output vs. address level relation for a logic AND gate assembled from two-diode and one-
crossed NW-FET. The inset in (d) shows the experimental truth table for the nano-AND gate. (e,f) Schematic and
measured output vs. address level relation for a logic NOR gate assembled from three-crossed NW-FET. The inset
in (f) shows the experimental truth table for the nano-NOR gate. (g,h) Schematics for a logic XOR gate and logic
half adder realized by interconnecting individual logic gate elements. Significantly, the logic half adder assembled
this way can be used to do digital computation just as conventional electronics do. Adapted from [30].
ample, NW logic gates have been interconnected to form an XOR gate and a logic half adder, which
was used to carry out digital computations in a way similar to conventional electronics (Figs. 6g,h).
Fig. 7 NanoLED. (a) Crossed InP nanowire LED. (top) Three-dimensional (3D) plot of light intensity of the
electroluminescence from a crossed NW LED. Light is only observed around the crossing region. (bottom) 3D
atomic force microscope image of a crossed NW LED. (inset) Photoluminescence image of a crossed NW junction.
(b) Multicolor nanoLED array. Schematic of a tri-color nanoLED array assembled by crossing one n-GaN, n-CdS,
and n-CdS NW with a p-Si NW. The array was obtained by fluidic assembly and photolithography with ca. 5 µm
separation between NW emitters. (c) Normalized EL spectra obtained from the three elements. (d) Integrated as a
nanoFET-nanoLED array. Schematic of an integrated crossed NW-FET and LED. Inset shows SEM image of a
representative device (scale bar, 3 µm) and the equivalent circuit. (e) Plots of current and emission intensity of the
nanoLED as a function of voltage applied to the NW gate at a fixed bias of –6 V. (inset) EL intensity vs. time
relation a voltage applied to NW gate is switched between 0 and +4 V for fixed bias of –6 V. Adapted from [31].
like source, and moreover, comparison of EL and PL (inset, Fig.7a) images recorded on the same sam-
ple show that the position of the EL maximum corresponds to the crossing point in the PL image. These
data thus demonstrate that the emitted light indeed comes from the crossed NW p-n junction.
EL spectra (peaked 820 nm) recorded from the cNW-LEDs exhibit blue-shifts relative to the bulk
band gap of InP (925 nm). The blue-shifts are due in part to quantum confinement of excitons, although
other factors may also contribute. Furthermore, PL studies have demonstrated that the PL peak can be
systematically blue-shifted as the NW diameter is decreased [44], and thus these results provide a
means for controlling the color of the LEDs in a well-defined way. Indeed, EL results recorded from
p-n junctions assembled from smaller (and larger) diameter NWs show larger (smaller) blue-shifts. In
addition, the emission color from nanoLEDs can be further varied by using chemically distinct semi-
conductor NWs with different band gaps. Considering the wide range of group IV, III-V, and II-VI semi-
conductor NW materials available [25], it is possible to assemble a variety of NW-based nanoLEDs for
different spectral regimes [31]. Indeed, we have recently demonstrated that crossing p-type Si NWs
with n-type GaN, CdS, CdSeS, CdSe, and InP can produce nanoLEDs with emission spectra covering
the whole spectra regime from UV to near IR [31]. In such heterostructure devices, p-Si NWs are used
as the passive hole-injector, and the n-type compound NWs are used as electron-injector and active
emitter, which defines the wavelength of emission.
The bottom-up assembly approaches allows flexible combination of chemically distinct nanoscale
building blocks that would otherwise be structurally and/or chemically incompatible in a sequential
growth process typical of planar fabrication. This capability should enable assembly of nanostructures
with functions not readily obtained by other methods and open new opportunities. For example, we have
exploited the ability to form nanoLEDs with nonemissive Si NW hole-injectors to assemble multicolor
arrays consisting of n-type GaN, CdS, and CdSe NWs crossing a single p-type SiNW (Fig. 7b).
Normalized emission spectra recorded from the array demonstrate three spectrally distinct peaks with
maxima at 365, 510, and 690 nm (Fig. 7c) consistent with band edge emission from GaN, CdS, and
CdSe, respectively. The ability to seamlessly assemble/integrate different materials together and inde-
pendently tune the emission from each nanoLED offers substantial potential producing specific wave-
length sources, and demonstrates an important step toward integrated nanoscale photonic circuits.
Although lithography sets the integration scale of these multicolor arrays, it should be possible to cre-
ate much denser nanoLED arrays via (1) controlled growth of modulated NW superlattice structures
[54] and/or (2) selective assembly of different semiconductor materials [55].
In addition, we have assembled optoelectronic circuits consisting of integrated crossed NW LED
and FET elements (Fig. 7d). Specifically, one GaN NW forms a p-n diode with the SiNW, and a sec-
ond GaN NW functions as a local gate as described previously. Measurements of current and emission
intensity vs. gate voltage show that (i) the current decreases rapidly with increasing voltage as expected
for a depletion mode FET and (ii) the intensity of emitted light also decreases with increasing gate volt-
age. When the gate voltage is increased from 0 to +3 V, the current is reduced from ca. 2200 nA to an
off state, where the supply voltage is –6 V (Fig. 7e). Advantages of this integrated approach include
switching with much smaller changes in voltage (0 to 3 vs. 0 to 6 V) and the potential for much more
rapidly switching. The ability to use the nanoscale FET to switch reversibly the nanoLED on and off
has also been demonstrated (inset, Fig. 7e).
The potential of coupling the bottom-up assembly of nanophotonic devices together with top-
down fabricated silicon structures has also been investigated, since this coupling could provide a new
approach for introducing efficient photonic capabilities into integrated silicon electronics. To this end,
a hybrid top-down/bottom-up approach was employed (1) using lithography to pattern p-type silicon
wires on the surface of a silicon-on-insulator (SOI) substrate, and then (2) assembling n-type emissive
NWs on top of silicon structures to form arrays consisting of p-n junctions at cross-points (Fig. 8a).
Conceptually, this hybrid structure (Fig. 8b) is virtually the same as the crossed NW structures de-
scribed above and should produce EL in forward bias. Notably, I-V data recorded for a hybrid p-n diode
formed between the p-Si and an n-CdS NW show clear current rectification (Fig. 8c) and sharp EL spec-
Fig. 8 Integration of nanowire photonics with silicon electronics. (a) Schematic illustrating fabrication of hybrid
structures. A silicon-on-insulator (SOI) substrate is patterned by standard electron-beam or photolithography
followed by reactive ion etching. Emissive NWs are then aligned onto patterned SOI substrate to form photonic
sources. (b) Schematic of a single LED fabricated by the method outlined in (a). (c) I-V behavior for a crossed p-n
junction formed between a fabricated p+-Si electrode and an n-CdS NW. (d) EL spectrum from the forward-biased
junction. (e) SEM image of a CdS NW assembled over seven p+-silicon electrodes on an SOI wafer; scale bar is
3 µm. (f) EL image recorded from an array consisting of a CdS NW crossing seven p+-Si electrodes. The image
was acquired with +5 V applied to each silicon electrode while the CdS NW was grounded. Adapted from [31].
trum peaked at 510 nm (Fig. 8d), which is consistent with CdS band edge emission. Importantly, the
photonic devices produced in this approach are highly reproducible and can be readily implemented in
integrated arrays. For example, a 1 × 7 crossed array consisting of a single CdS NW over 7-fabricated
p-Si wires (Fig. 8e) exhibits well-defined emission from each of the cross-points in the array (Fig. 8f).
Similar results were also obtained for two-dimensional arrays and demonstrate clearly that bottom-up
assembly has the potential to introduce photonic function into integrated silicon microelectronics.
can function as a single-mode optical waveguide much like a conventional optical fiber [58] when
1 ~ (πD/λ)(n12–n02)0.5 < 2.4, where D is the NW diameter, λ is the wavelength, and n1 and n0 are the
refractive indices of the NW and surrounding medium, respectively (Fig. 9a, see color plate, p. 2059).
If the ends of the NW are cleaved (Fig. 9b), they can function as two reflecting mirrors that provide op-
tical feedback and define a Fabry–Perot optical cavity with modes m(λ/2n1) = L, where m is an integer
and L is the length of the cavity. Photoluminescence image of CdS NWs of proper diameter shows pro-
nounced emission from both ends (Fig. 9c), clearly demonstrating waveguide effect along the NW axis.
Furthermore, spectra of the emissions from NW ends show prominent periodic modulation in intensity,
which can be attributed to the longitudinal modes of a Fabry–Perot cavity (Fig. 9d). For a cavity of
length L, the mode spacing, ∆λ, is given by (λ2/2L)[n1–λ(dn1/dλ)]–1, where dn1/dλ is the dispersion re-
lation for the refractive index. This expression provides a good description of the observed spacing
when the measured nanowire length. Moreover, analysis of similar data from NWs of varying length
demonstrates that the mode spacing is inversely proportional to the wire length as expected. Together,
these results demonstrate that the individual NW can function as nanoscale optical waveguide and
Fabry–Perot cavity. The observation of sharp modes in the uniform CdS NW gain medium suggests a
single NW can support laser emission. Indeed, optical excitation at higher powers leads to preferential
gain in a single mode and the onset of lasing (Fig. 9e).
The observation of laser emission with optical excitation further prompts us to investigate elec-
trically pumped nanolasers. To achieve electrical pumped lasers requires efficient injection of both elec-
trons and holes into the NW cavity and gain medium. Our initial studies of electrical injection into CdS
NW cavities were carried out using an n-type CdS and p-type silicon (p-Si) crossed NW structures
(Figs. 10a,b, see color plate, p. 2059). In forward bias, these crossed NW structures exhibit strong elec-
troluminescence with several important characteristics. Images of the electroluminescence (Figs. 10c,d)
show two points of emission: one corresponding to the n-CdS/p-Si NW cross-point and the other to the
end of the CdS NW. Significantly, the intensity of the end emission is at least two orders of magnitude
larger than the cross-point emission. Further more, EL spectra recorded from the CdS NW end exhibit
a prominent modulation in intensity, which can be assigned to the longitudinal modes of a Fabry–Perot
cavity formed in CdS NW in this crossed device (Fig. 10e). These results clearly demonstrating that the
CdS NWs can function as excellent waveguides and Fabry–Perot cavity in this relatively simple device
configuration, and suggest that at sufficiently high injection currents lasing should be achieved.
However, the crossed NW devices are clearly not optimal for achieving high-density injection into the
whole NW cavity, as high injection current invariably led to breaking down of the device at the cross-
point due to the nature of localized injection.
To enable more uniform injection, we have implemented a hybrid structure (Figs. 10f,g) in which
holes are injected along the length of a CdS NW cavity from a p-Si electrode defined in a heavily doped
p-Si layer on a planar substrate [32]. Images of the room-temperature electroluminescence produced in
forward bias from these structures (Fig. 10h) show strong emission from the exposed CdS NW end.
Low-temperature measurements made on the devices have shown the preferential pumping into single
mode. At low injection currents, the spectrum of the end emission (Fig. 10i) shows a broad peak with
FWHM ~5 nm. Significantly, when the injection current is increased further, it was found that the emis-
sion intensity increased abruptly, and the spectrum quickly collapsed into a limited number of sharp
peaks with a dominant emission line around 493 nm. Importantly, we find that the dominant mode has
an instrument resolution limited line width of only 0.7 nm, demonstrating that the injection lasing is
achieved in this new type of device. Using individual NWs as the laser cavity and gain medium for laser
diodes represents a new and powerful approach for producing integrated electrically driven photonic de-
vices. This basic approach, which relies upon bottom-up assembly of the key laser cavity/medium in a
single step, can be extended to other materials, such as GaN and InP NWs, to produce nanoscale lasers
that not only cover the ultraviolet through near infrared spectral regions, but also can be integrated as
single or multi-color laser source arrays in silicon microelectronics and lab-on-a-chip devices.
Fig. 11 Nanophotonics as excitation source. (a) Solid line is the emission spectrum recorded from CdSe QDs
excited using a p-Si/n-CdS NW nanoLED; the QD emission maximum was 619 nm. The increasing intensity on
the shorter wavelength side of the emission peak corresponds to the tail of the CdS nanoLED. Dashed line is the
spectrum of pure CdSe QDs excited using an Ar-ion laser. (b) Solid line is the emission spectrum from propidium
iodide excited using a p-Si/n-CdS NW nanoLED. Dashed line is emission spectrum of propidium iodide obtained
in aqueous solution (Fluorolog, ISA/Jobin Yvon-Spex). Adapted from [31].
and possibly conceptually and fundamentally new types of devices such as single photon emitters and
detectors, which could be critical for future quantum communication and computation. Continuing ef-
forts will be required to develop even better control of NW synthesis and more and more sophisticated
assembly approaches that can vary device functionality over multi-length scales. Lastly, developing new
device concepts and integrated architectures will be increasingly essential as we move closer to ultra-
high-density, integrated nanosystems.
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