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Learning Objectives
Computer architecture
Components of a simple central processing unit:
o o
registers, ALU, control unit and buses Buses, clocks, peripheral devices, memory
Features of computers
Speed and reliability Components and CPU registers Memory organization
Fetchdecodeexecute cycle and its use to Fetch decode execute instructions in a simple computer
Peripheral Devices
Memory
Arithmetic-logic unit (ALU) ArithmeticCarries out logical and arithmetic operations Often affects the status register (e.g., overflow, carry) Operations are controlled by the control unit
Main Memory
Holds programs and data Stores bits in fixed-sized chunks: word (8, 16, fixedword 32 or 64 bits) Each word has a unique address The words can be accessed in any order random-access memory or RAM randomRAM
Memory
Consists of a linear array of addressable storage cells
A memory address is represented by an unsigned integer Can be byte-addressable or word-addressable bytewordByte-addressable: each byte has a unique address ByteWord-addressable: a word (e.g., 4 bytes) has a unique Wordaddress
Memory: Example
A memory word size of a machine is 16 bits A 4MB 16 RAM chip gives us 4 megabytes of 16-bit memory locations 164MB = 22 * 220 = 222 = 4,194,304 unique locations (each location contains a 16-bit word) 16Memory locations range from 0 to 4,194,303 in unsigned integers
Hardware Components of a Typical Computer Peripheral Devices that Communicate with the Outside World
Peripheral Devices Central Processing Unit (CPU) Memory
Input/Output (I/O)
Input: keyboard, mouse, microphone, scanner, sensors (camera, infra-red), punch-cards infrapunchOutput: video, printer, audio speakers, etc
Communication
modem, ethernet card
Hardware Components of a Typical Computer Peripheral Devices that Store Data Long Term
Secondary (mass) storage Stores information for long periods of time as files
Examples: hard drive, floppy disk, tape, CDCDROM (Compact Disk Read-Only Memory), flash Readdrive, DVD (Digital Video/Versatile Disk)
Memory
Buses
Physically a bus is a group of conductors that allows all the bits in a binary word to be copied from a source component to a destination component Buses move binary values inside the CPU between registers and other components Buses are also used outside the CPU, to copy values between the CPU registers and main memory, and between the CPU registers and the I/O sub-system sub-
Clock
Every computer contains at least one clock that synchronizes the activities of its components
A fixed number of clock cycles are required to carry out each data movement or computational operation The clock frequency determines the speed of all operations
o
Clock-speed CPU-performance ClockCPUThe CPU time required to run a program is given by the general performance equation:
But, in general
Multiplication takes longer than addition Floating point operations require more cycles than integer operations Accessing memory takes longer than accessing registers
Reliability
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CPU Speed
CPU clock speed: in cycles per second ("hertz")
Example: 700MHz Pentium III, 3GHz Pentium IV
but different CPU designs do different amounts of work in one clock cycle Other measures of speed
flops (floating-point operations per second) flops (floatingmips (million instructions per second) mips
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Memory-Access Speed
RAM
about 60ns (1 nanosecond = a billionth of a second), and getting faster may be rated with respect to bus speed (e.g., speed PC-100) PC-
Cache memory
faster than main memory (about 20ns access speed), but more expensive contains data which the CPU is likely to use next
Communications
Examples: modems at 56 kilobits per second, and network cards at 10 or 100 megabits per second
I/O
Examples: ISA, PCI, IDE, SCSI, ATA, USB, etc....
12
Each type of interrupt or exception is associated with a procedure that directs the actions of the CPU
13
Fetch-decode-execute Cycle
A computer runs programs by performing fetch-decode-execute cycles
fetch next instruction from memory ( word pointed to by PC ) and place in IR decode instruction in the IR to determine type execute instruction go to the next instruction (next word in memory)
Example: instruction word Example: at mem[PC] is 0x20A9FFFD mem[PC]
Opcode 8 is add immediate, immediate source reg is $5, target reg $5, target is reg $9, add amount is 3 $9, Send reg $5 and -3 to ALU, add them, put result in reg $9 PC = PC + 4
14
Memory Segments
Memory is organized into segments, each with its own segments, purpose
0x00000000 0x00400000 0x10000000 reserved for OS text segment data segment (heap) heap) stack segment reserved for the Operating System (OS) kernel code users code user free space, grows and shrinks as stack/data segments change kernel code and data
memory addresses
0x80000000
0xFFFFFFFF
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Text Segment
Starts at memory address 0x00400000 runs up to address 0x0FFFFFFF Contains users executable program code (often called the code segment ) PC register value is a CPU reference into this memory segment
Data Segment
Starts at memory address 0x10000000 expands upwards towards stack Contains programs static data, i.e., data and program data, variables whose location in memory is fixed (and known to the assembler)
In C global variables string constants In Java public, static objects
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Stack Segment
Starts at memory address 0x7FFFFFFF
grows in the direction of decreasing memory addresses ( i.e., towards the data segment)
Heap
Technically part of data segment
located at end of data segment, after all static data
Empty at start of program execution Dynamically allocated memory is taken from heap for program to use Freed memory (by user or garbage collection) is returned to heap
17
INPUT 1001100101001
A typical schematic symbol for an ALU: A & B are operands; R is the output; F is the input from the Control Unit; D is an output status
18
Control Unit
A computers control unit keeps things computer synchronized
Makes sure that the correct components are activated as the components are needed Sends bits down control lines to trigger events
o
E.g., when Add is performed, the control signal tells the ALU to Add
How do these control lines become asserted? o Hardwired control: controllers implement this control: program using digital logic components o Microprogrammed control: a small program is control: placed into read-only memory in the microcontroller read-
19
20
Registers
A register is a single, permanent storage location within the CPU used for a PARTICULAR, defined purpose purpose A register is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations calculations Registers have special addresses
Output Data
CPU Cycle
Fetch an instruction from the memory cell where the PC points
. .
Bus
Decode the instruction
ALU
Execute the instruction
Control Unit
CPU
Increment the PC
21
Registers
CPU Arithmetic/ Logic Unit Rn Control Unit R0 BUS R1 Main Memory Secondary Storage Input devices Output devices
Registers are used to hold the data immediately applicable to the operation at hand; Main memory is used to hold the data that will be needed in the near future Secondary storage is used to hold data that will be likely not be needed in the near future
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R1 10011001 R2 01101101
LOAD R A LOAD R11 ,, A LOAD R B LOAD R22 ,, B ADD ADD R R R R00 ,, R11 ,,R22
A+B
R0 01010100
Load the first number from memory cell A into register R1 Load the second number from memory cell B into register R2 Adding the numbers in these two registers and put the result in register R0 Store the result in R0 into the memory call X
23
Instruction Fetch
The address in the Program Counter is placed in MAR The addressed instruction is read from memory (through the MDR) and placed into the Instruction Register
Instruction Execute
The Instruction Decoder examines the instruction in the Instruction Register and sends appropriate signals to other parts of the CPU to carry out the actions specified by the instruction. This may include:
Reading operands from memory or registers into the Arithmetic Logic Unit, Unit, Enabling the circuits of the Arithmetic Logic Unit to perform arithmetic or other computations, Storing data values into memory or registers, Changing the value of the Program Counter
24
25
26
Features of two machine instruction sets (CISC and RISC) Instruction format
53
27
Operands
type (addresses, numbers, characters) and access mode location (CPU or memory) organization (stack or register based) o number of addressable registers
Memory organization
byte- or word-addressable byte- word-
28
29
Machine Instructions
Data Transfer: transfer data between registers and memory cells Arithmetic/Logic Operations: perform addition, AND, OR, XOR and etc. Control Operations: control the execution of the program
30
L 1 30 L 1 ,, 30 L 2 40 L 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
/*Load R with the content /*Load R11with the content in memory cell 30 */ in memory cell 30 */ /* Load R with the content /* Load R22with the content in memory cell 40 */ in memory cell 40 */ /* Store R to 40 */ /* Store R11to 40 */ /* Store R to 30 */ /* Store R22to 30 */
40
10011010
R1 01101101 R2 10011010
31
L 1 30 L 1 ,, 30 L 2 40 L 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
/*Load R with the content /*Load R11with the content in memory cell 30 */ in memory cell 30 */ /* Load R with the content /* Load R22with the content in memory cell 40 */ in memory cell 40 */ /* Store R to 40 */ /* Store R11to 40 */ /* Store R to 30 */ /* Store R22to 30 */
40
R1 01101101 R2 10011010
ADD the numbers in R1 and R2 representing in 2s 2 complement and place the result in R0 ADD the numbers in R1 and R2 representing in floatingfloatingpoint and place the result in R0
32
Memory
10011001 01101101 = -25 = 109
X0
01010100
= 84
Registers
7. OR R0, R1, R2
OR the bit patterns in R1 and R2 and place the result in R0 AND the bit patterns in R1 and R2 and place the result in R0
9. XOR R0, R1, R2 XOR the bit patterns in R1 and R2 and place the result in R0
33
X0
00001011
Registers
R0 R1 10011011 R2 00001111
R0 R1 R2
R0 R1 R2 R3 R4
10011001 11011011 00001111 11110000
34
B. RR R , I
ROTATE the bit patterns in R to right I times. Each time place the bit that started at the low-order end at the highlowhighorder end
1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0
Example RR , 0 , 02
Original String
Resulting String
Control Instructions
E. JMP R , A JUMP the instruction located in the memory cell A if the bit pattern in R is equal to the one in R HALT the execution
F. HALT
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30 32 34 36 38 3A 3C 3E
LI 0 0A LI 0 ,, 0A LI 1 00 LI 1 ,, 00 LI 2 01 LI 2 ,, 01 ADD 3 1, 2 ADD 3 ,, 1, 2 JMP 3 3E JMP 3 ,, 3E LR 1 3 LR 1 ,,3 JMP 0 36 JMP 0 ,,36 HALT HALT R0 R1 R2 R3
00001010 00000000 00000001 00000001
R0 = 0A R1 = 00 R2 = 01 R3 = R1 +R2
Yes
R3 = R0 ?
No
R1 = R3
Program Counter
8 bit bus
Circuits
Code Segment
A d d r e s s
30 3C 48 54 74 80 8C 98
21 23 11 12 17 FF 82 81 31 94 22 31 80 23 80 7F 21 23 83 31 F5 01 12 80 31 52 20 12 81 34 00 7F 11 53 E3 32 80 12 5E 81 12 33 11 F0 81 82 80 00
Main Memory
Data Segment
ALU
36
Operand Organization
Three choices
Accumulator architecture General Purpose Register (GPR) architecture Stack architecture
Disadvantage
Memory traffic is very high Programming is cumbersome
37
Disadvantage
Results in longer instructions (longer fetch and decode times)
38
Example:
POP PUSH 9
5 9 7 2
Advantage
Good code density Simple model for evaluation of expressions
Disadvantage
Restricts the sequence of operand processing Execution bottleneck (the stack is located in memory)
39
in a stack ISA
Binary operators pop the two operands on the stack top, and push the result on the stack
40
The first operand is often the destination for the result of the instruction
41
Coding Instruction
16 bit Instruction (2 bytes)
High-Order Byte HighLow-Order Byte Low-
1
LI
1
4
1
7C
Instruction Formats
16 bit Instruction (2 bytes) Format 1 Format 2 Format 3 Format 4 Register Register Register Immediate Value Memory Address Register Register Register
42
Format 1 Instruction
Format 1 Instruction Format 1 Register Immediate Value
Opcode
2 A B C D
Instruction LI R , I
Meaning
Load Immediate Rotate Left Rotate Right Shift Left Shift Right
RL RR SL SR
R , I R , I R, I R , I
Format 1 Instruction
Format 1 Register Immediate Value
1. COPY THE BIT PATTERN IN THE LOW-ORDER BYTE LOWINTO THE SPECIFIED REGISTER , OR 2. SHIFT/ROTATE THE BITS IN THE SPECIFIED REGISTER THE NUMBER OF PLACES SPECIFIED IN THE LOW-ORDER BYTE. LOW-
43
Format 2 Instruction
Format 2 Instruction Format 2 Register Memory Address
Opcode
Instruction
Meaning
Load from Memory Store to Memory Conditional Jump
1 3 E
L R , A ST R , A JMP R , A
Format 2 Instruction
Format 2 Register Memory Address
1. Load - Copy the value stored at the Memory Address into the specified register 2. Store - Copy the value in the specified register to the Memory Address 3. Jump - Compare the contents of the specified register and the contents of Register 0. If equal reset the Program Counter to the Memory Address
44
Format 3 Instruction
Format 3 Instruction Format 3 Register Register Register
Opcode
5
6
Meaning
Load Immediate Rotate Left Rotate Right Shift Left Shift Right
7 8 9
R 0, R 1, R 2 R 0, R 1, R 2 R 0, R 1, R 2 R 0, R 1, R 2
Format 3 Instruction
Format 3
Register
Register
Register
Apply the operation to the two values in the registers specified in the Low-Order byte and store the result in the Lowregister specified in the High-Order byte High-
45
Format 4 Instruction
Format 4 Instruction
Format 4
Register
Opcode
Instruction
Meaning
Load Register
LR R1 , R2
Format 4 Instruction
Format 4
Register
Copy the value in the second register specified in the Low-Order byte to the first register specified in the LowLow-Order byte Low-
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2. LI R 2. LI R ,, II 3. ST R A 3. ST R ,, A R 4. LR R 4. LR R11,, R22 5. ADD R R, R 5. ADD R00,, R11, R22 R, R 6. AFP R 6. AFP R00,, R11, R22 7. OR 7. OR R R, R R00,, R11, R22
Examples of OpCode
Name MOV PUSH POP IN OUT Comment TRANSFER Move (copy) Push onto stack Pop from stack Input Output ARITHMETIC Add Subtract Divide (unsigned) Multiply (unsigned) Increment Decrement Compare Syntax MOV Dest,Source PUSH Source POP Dest IN Dest, Port OUT Port, Source
ADD Dest,Source SUB Dest,Source DIV Op MUL Op INC Op DEC Op CMP Op1,Op2
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Examples of OpCode
Name NEG NOT AND OR XOR Comment Syntax LOGIC Negate (two-complement) NEG Op (twoInvert each bit NOT Op Logical and AND Dest,Source Logical or OR Dest,Source Logical exclusive or XOR Dest,Source JUMPS Call subroutine Jump Jump if Equal Jump if Zero Return from subroutine Jump if not Equal Jump if not Zero
CALL Proc JMP Dest JE Dest JZ Dest RET JNE Dest JNZ Dest
30
0110 1101
R1 R2
30 40
40
1001 1001
48
DECODE EXECUTE
1.
Increment the PC
Execute
Fe tc h
Retrieve the next instruction from memory (as indicated by the program counter) and then increment the program counter
2.
D e od ec
3.
R0 R1 R2 .. RF
L L L L
1 30 1 ,, 30 2 40 2 ,, 40
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
49
Execute a Program
PC
FETCH DECODE EXECUTE
10 11 12 13 14 15 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
30 40
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
PC
FETCH DECODE EXECUTE
10 11 12 13 14 15 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
16 17
50
Execute a Program
PC
FETCH DECODE EXECUTE
10 11 12 13 14 15 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
PC
FETCH DECODE EXECUTE
10 11 12 13 14 15 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
0110 1101
16 17
51
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
0110 1101
11
PC
12 13 14 15
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
0110 1101
11
PC
12 13 14 15
16 17
30 40
52
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
0110 1101
11
PC
12 13 14 15
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2 .. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
0110 1101
11
PC
12 13 14 15
16 17
53
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11
PC
12 13 14 15
.. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13
PC
14 15 16 17
.. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
30 40
54
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13
PC
14 15
.. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
30 40
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13
PC
14 15
.. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
16 17
55
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13
PC
14 15
.. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13
PC
14 15
.. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
16 17
56
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13 14 15
PC
.. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
30 40
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13 14 15
Instruction:
PC
.. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
16 17
30 40
57
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13 14 15
Instruction:
PC
.. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13 14 15
Instruction:
PC
.. RF L L L L 1 30 1 ,, 30 2 40 2 ,, 40 ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
16 17
58
Execute a Program
10 0001 0001 0011 0000 0001 0010 0100 0000 0011 0001 0100 0000 0011 0010 0011 0000
R0 R1 R2
0110 1101 1001 1001
11 12 13 14 15
Instruction:
PC
.. RF L L L L 1 1 ,, 2 2 ,, 30 30 40 40
16 17
ST 1 40 ST 1 ,, 40 ST 2 30 ST 2 ,, 30
30
1001 1001
R1 R2
40
0110 1101
59
LI 1 17 LI 1 ,, 17 ST 1 A ST 1 ,, A LI 1 F5 LI 1 ,, F5 ST 1 B ST 1 ,, B
LOAD 23 IN HEX INTO R1 LOAD 23 IN HEX INTO R1 STORE VALUE AT A STORE VALUE AT A LOAD 11 IN HEX INTO R1 LOAD --11 IN HEX INTO R1 STORE VALUE AT B STORE VALUE AT B
LI 1 17 LI 1 ,, 17 ST 1 A ST 1 ,, A LI 1 F5 LI 1 ,, F5 ST 1 B ST 1 ,, B
00100001 00010111 00100001 00010111 00110001 10000000 00110001 10000000 00100001 11110101 00100001 11110101 00110001 10000001 00110001 10000001
60
ADD 2 3 4 5234 ADD 2 ,, 3 ,, 4 5234 ADD 3 1 2 5312 ADD 3 ,, 1 ,, 2 5312 ST 3 C ST 3 ,, C 3382 3382
61
Example Program
PROGRAM Sort; VAR A,B,C : INTEGER; PROCEDURE Swap (VAR X,Y : INTEGER); VAR Temp : INTEGER; BEGIN {Swap} Temp := A; A := B; B := Temp; END {Swap}; BEGIN {Sort} C := A-B; AIF C = 0 THEN Swap (A,B); END {Sort}.
62
30 3C 48 54 74 80 8C 98
21 23 11 12
17 FF 82 81
31 94 22 31
80 23 80 7F
21 23 83 31
F5 01 12 80
31 52 20 12
81 34 00 7F
11 53 E3 32
80 12 5E 81
12 33 11 F0
81 82 80 00
Program Counter
Instruction Register
Main Memory
Data Segment
ALU
63
30
Main Memory
ALU
30
21
21
Main Memory
ALU
64
30
21 17 21
17
Main Memory
ALU
32
21 17 21
Main Memory
ALU
65
32
LI
21 17 21
Main Memory
ALU
32
LI
21 17 21
17
Main Memory
ALU
66
32
31 17 21
31
17
Main Memory
ALU
32
31 80 21
80
17
Main Memory
ALU
67
34
31 80 21
17
Main Memory
ALU
34
31 80 21
ST
17
17
ALU
Main Memory
68
34
31 80 21
ST
17
17
17
ALU
Main Memory
34
21 80 21
21
17
74 80 17 8C 98
Main Memory
ALU
69
34
21 F5 21
F5
17
74 80 17 8C 98
Main Memory
ALU
36
21 F5 21
17
74 80 17 8C 98
Main Memory
ALU
70
36
21 F5 21
LI
17
74 80 17 8C 98
17
ALU
Main Memory
36
21 F5 21
LI
17
74 80 17 8C 98
F5
ALU
Main Memory
71
36
31 F5 21
31
30 3C 48 54
21 23 11 12 17 FF 82 81 31 94 22 31 80 23 80 7F 21 23 83 31 F5 01 12 80 31 52 20 12 81 34 00 7F 11 53 E3 32 80 12 5E 81 12 33 11 F0 81 82 80 00
F5
74 80 17 8C 98
Main Memory
ALU
36
31 81 21
81
30 3C 48 54
21 23 11 12 17 FF 82 81 31 94 22 31 80 23 80 7F 21 23 83 31 F5 01 12 80 31 52 20 12 81 34 00 7F 11 53 E3 32 80 12 5E 81 12 33 11 F0 81 82 80 00
F5
74 80 17 8C 98
Main Memory
ALU
72
38
31 81 21
F5
74 80 17 8C 98
Main Memory
ALU
38
31 81 21
ST
F5
74 80 17 8C 98
F5
ALU
Main Memory
73
38
31 81 21
ST
F5
74 80 17 8C 98
F5
F5
ALU
Main Memory
38 11
11 81 21
30 3C 48 54
21 23 11 12
17 FF 82 81
31 94 22 31
80 23 80 7F
21 23 83 31
F5 01 12 80
31 52 20 12
81 34 00 7F
11 53 E3 32
80 12 5E 81
12 33 11 F0
81 82 80 00
F5
74 80 17 F5 8C 98
Main Memory
ALU
74
38 80
11 80 21
30 3C 48 54
21 23 11 12
17 FF 82 81
31 94 22 31
80 23 80 7F
21 23 83 31
F5 01 12 80
31 52 20 12
81 34 00 7F
11 53 E3 32
80 12 5E 81
12 33 11 F0
81 82 80 00
F5
74 80 17 F5 8C 98
Main Memory
ALU
3A
11 80 21
F5
74 80 17 F5 8C 98
Main Memory
ALU
75
3A
11 80 21
L
F5
74 80 17 F5 8C 98
17
Main Memory
ALU
3A
11 80 21
L
F5
74 80 17 F5 8C 98
17
17
ALU
Main Memory
76
21
L
F5
74 80 17 F5 8C 98
Main Memory
ALU
77
78
Speedup
n k tp ( k + n 1) t p
79
Thank You
80