JOURNAL OF COMPUTING, VOLUME 4, ISSUE 1, JANUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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Performance Comparison of 3D-Mesh and 3D-Torus Network-on-Chip

Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract The widely used NoC topologies are Mesh and Torus architecture. We analyses performance of three-dimensional Mesh and Torus based NoC with 64 resources and switches in presence of permanent faults With IP routing. We also carry out the high-level simulation of on chip network using NS-2 to verify the analytical analysis. Index Terms NoC (Network on chip), performance, 3D-mesh, 3D-torus.

1 INTRODUCTION
Future integrated systems will contain billion of transistors [1], composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network applications, should be able to deliver rich multimedia and networking services. An efficient communication among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. An architecture that is able to accommodate such a high number of cores, satisfying the need for communication and data transfers, is the Network-on-Chip (NoC) architecture [2],[ 3]. With the increasing complexity of multiprocessor systemson chip (MPSoC), global communication on chip has become a major challenge for system performance improvement within restricted power and area budgets [4]. Networks on chip (NoCs) are emerging as an alternative to existing dedicated interconnection and shared bus [5] [6]. It relieves on-chip communication issues by improving the bandwidth, power efficiency and scalability [7]. The NoC design methodology was proposed relatively recently [8], [9] and [10], and is still a developing research area with many open problems. At first, NoC research focused on trying to port ideas from the fields of networking and parallel computing to the realm of VLSI. It became apparent that this approach was infeasible because NoCs and traditional networks exist in two different environments with conflicting requirements. SoCs differ from traditional networks because of local proximity and because they exhibit much less non-determinism [11]. On-chip network topology is a crucial factor of the chip in terms of performance, cost, and energy consumption. Various network topologies have been studied for NoCs. Especially, two-dimensional mesh [12] and torus [13] are popularly used in NoCs, because their grid-based regular arrangement is intuitively considered to be matched to the two-dimensional VLSI layout.

2 BACKGROUND
Networks-on-Chips are becoming more and more popular as a solution able to accommodate large numbers of IP cores, offering an efficient and scalable interconnection network. Three-dimensional NoCs are taking advantage of the progress of integration and packaging technologies offering advantages when compared to 2D ones. Existing 3D NoCs assume that every router of a grid can communicate directly with the neighboring routers of the same grid and with the ones of the adjacent planes. This communication can be achieved by employing wire bonding, through-silicon. Furthermore, the emerging three-dimensional (3D) integration and process technologies allow the design of multi-level Integrated Circuits (ICs). As illustrated in [14], this creates new design opportunities in NoC design. In order to satisfy the demands of emerging systems for scaling, performance and functionality 3D integration is a way to accommodate these demands [15]. For example, a considerable reduction can be achieved in the number and length of global interconnect using three-dimensional integration. On deciding whether to choose a twodimensional (2D) or 3D NoC as an architecture it is shown in [16],[17] that 3D NoCs are advantageous, providing better performance.

2.1 3D-NOC-Torus
3D NoCs combining both the benefits soon become one of the most promising on-chip communication techniques in complex System-on-Chip(SoC) [18],[19]. In addition to NoC architecture, three-dimensional integrated circuit (3D IC) offers an attractive solution for overcoming the barriers to interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology, with smaller form factor, higher integration density, and the support for the realization of mixed-technology chips Among several 3D

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integration [20]. To combine the benefits of NoCs and 3D ICs, 3D NoCs have been proposed in [21] to offer better performance, especially for 3D network topologies. B. S. Feero et al. demonstrated that the 3D realization of both mesh and tree-based NoCs could improve the performance significantly by reducing interconnects length. In this paper, we develop a consistent and meaningful evaluation methodology to evaluate the performance of a variety of 3D NoC architectures compared to existing 2D counterparts. Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. Topology selection is a NoC design issue which needs to be addressed in the early design stages and which has deep implications both on final system performance and on physical network feasibility. NoC architectures can be designed with both regular and custom topologies. The primary advantages of a regular NoC architecture are topology reuse, reduced design time, ease of routing, better control of electrical parameters and hence less design respins and a higher degree of performance predictability. The 2D mesh is currently the most popular regular topology used for on-chip networks in tile based architectures, because it perfectly matches the 2D silicon surface. Unfortunately, 2D meshes show very poor scalability properties in terms of diameter, average minimal hop count and bisection bandwidth.

sign of 3D NoCs. Feero et al. compared both 2D Mesh and 2D Torus to 3D Mesh and 3D stacked Mesh [35]. Results showed that 3D NoCs offer more competitive performance and energy consumption for communication. Li et al. introduced a 3D NoC by hybriding a common NoC router with a bus link in vertical dimension. The hybrid system allows single-hop communication between nodes connected by the vertical bus, and it provides both performance and area benefits [36].

2.3 Quality of Service in Network on Chip

Network on Chip is likely to become an attractive alternative for implementing SoCs for many application areas like real time multi-media applications. This implies that the underlying on-chip communication network will be required to provide deterministic bounds on delays and throughput for communication among some pairs of cores on the chip [37].

3 NETWORK AND ARCHITECTURE

3.1 Topology and Hardware Architectures
Two different network topologies have simulated namely the 3D-mesh and 3D-torus. 3D topologies built from 4x4x4 routers. As shown in Fig .1 and Fig .2, the square nodes stand in IPs and the circle nodes stand in switches. These topologies easily scaled to different sizes.

2.2 Related Work

The placement and routing in 3D integrated circuits are studied by Ababei et al. [22]. Also, a system on package solution for 3D network is presented by Lim [23]. However, the heat dissipation of 3D circuits remains a big challenge [24]. To tackle this challenge, several analysis techniques have been proposed [2527]. One approach is to perform thermal-aware placement and mapping for 3D NoCs, such as the work presented by Quaye [28]. Furthermore, the insertion of thermal vias can lower the chip temperature as illustrated in several texts [29],[30]. To combine the benefits of NoCs and 3D ICs, 3D NoCs have been proposed in [31]. to offer better performance, especially for 3D network topologies. The 3D realization of both mesh and tree-based NoCs could improve the performance signicantly by reducing the interconnects length. Due to the manufacturing challenges, multiplelayer 3D NoCs may be not practical at this moment. But the two-layer 3D realization has already improved the performance greatly. Although widely used across a number of network on chip (NoC) designs [32], [33], the 2D-mesh NoC topology lacks of scalability and tends to concentrate traffic in the center nodes [34]. This has motivated works in the open literature that come up with optimized NoC topologies while keeping regularity properties as much as possible. Several prior work has investigated the architecture de-

Fig . 1. Three-Dimensional Torus 4*4*4 NoC.

Another topolgy that we consider for simulation was a Mesh 4*4*4 Noc that shown in Fig .2, the number of resources and switces in both topologies was equal to 64.

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SIMULATION RESULTS

The simulation results of in Fig 3-6. The NoC topologies that tested were 3D-Mesh and 3D-Torus ones of 64 nodes. In this section four parameters communication load, Fault-Tolerant, End to End Delay and Hop count was consider for evaluation performance of mentioned topologies.

6.1 Communication load We consider that two resources node-0 and node-127 communicate together that have the maximum distance in both topologies. As shown in fig 3, a permanent fault occurs in 1.2 seconds and the communication load between of mentioned resources was reduces.

Fig . 2.Three-Dimensional Mesh 4*4*4 NoC.

SIMULATION FRAMEWORK

We reduce all parameters as multiply of 1000 to support the simulation time. To compare of these architectures in term of packet forwarding we consider the bandwidth between all switches is one Megabit/Sec and the bandwidth between all resources and switches is ten times bigger than the bandwidth of switches to switches. We consider the traffic source for each communicated core is UDP. Also, the bandwidth of these two cores that needs was equal to one Megabit/Sec and the delay of switch-toswitch or resource-to-switch is equal to ten millisecond.

Fig . 3. Supported bandwidth in 3D Mesh and Torus NoC.

SIMULATION DETAILS

We would use the tool, Network Simulator ns-2 [38],[39]. Which has extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol, Routing algorithms. NS-2 is an open source, object-oriented and discrete event driven network simulator written in C++ and OTcl. It is a very common and widely used tool to simulate small and large area networks [40]. Because of likenesses between NoCs and networks, NS-2 has been a choice of many NoC researchers to simulate and view the behaviour of a NoC at a higher abstraction design. It has a huge variety of protocols and various topologies can create with little effort. Also, customized protocols for NoCs can easily incorporated into NS-2. The parameters for routers and links can easily scale down to reflect real situation on a chip. Based on this fact, we have successfully simulated a hundred node 2D mesh based NoC using our reliable protocol for safe delivery of packets.

6.2 Fault-Tolerant As shown in fig .4, when a permanent fault occurs in communication path, the number of lost packets is equal in the both architectures.

Fig . 4. Lost Packets in two architecture.

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Because of the more path between two cores in three dimentional topologies, when a permanent fault occur in our communication path, the traffic re-routed to the other path.

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6.3 End to End Delay

As shown in fig.5, the average end to end delay 3D-torus is less than 3D-mesh architecture. This means the data transfer in 3D-torus is faster than 3D-mesh architecture.

[5]

[6]

[7]

[8] Fig . 5. Average end to end delay in two architecture. [9]

6.4 Hop count

As shown in fig. 6, the 3D-Torus has fewer hop count related to 3D-mesh architecture. These hop count has not effect on fault or bandwidth. The hop count effects on the time of transfer data between resources.
[10]

[11]

[12]

[13]

[14] [15]

[16] Fig . 6. Average hop count in two architecture. [17]

CONCLUSIONS AND FUTURE WORK

This paper proposed a 3D NoC for MPSoC, using 3DMesh and 3D-Torus and the evaluation results show that using of 3D-Torus architecture absolutely achieves superior performance with fixed IP Numbers.

[18]

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