Microfabrication I MC

NANO III
Chapter: Micro- and nano-fabrication

Michel Calame Institut fr Physik, Klingelbergstrasse 82, 4056 Basel room: 1.20, 1st floor email: michel.calame@unibas.ch
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Outline
Introduction: overview, state of the art, semiconductor physics reminder Fabrication basics IC fabrication overview clean-rooms Silicon: from sand to wafer material deposition techniques lithography etching examples of devices: MEMS, NEMS Outlook: new and future techniques
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References
overview books 1. Introduction to Semiconductor Manufacturing Technology H. Xiao, Prentice-Hall, 2001. 2. Fundamentals of Microfabrication: The Science of Miniaturization M. Madou, 2nd ed., CRC Press, 2002 3. Nanoelectronics and Information Technology R. Waser ed., Wiley-VCH, 2003 4. VLSI Technology (more physical) SM. Sze, 2nd ed., McGraw-Hill, 1988
many web sites, e.g. www.memsnet.org/glossary see also companies web sites: Intel, Infineon, IBM, AMD,
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Introduction
1947, 23th December John Bardeen, Walter Brattain, William Schockley ATT Bell Labs first point contact transfer resistor
reconstitution: Aylesworth
http://www.pbs.org/transistor/
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Introduction
1958 Jack Kilby, Texas Instruments first IC (Integrated Circuit)
C. Esser, Infineon
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Introduction
1961, Robert Noyce, Fairchild Camera first integrated circuit available as a monolithic chip Planar technology (Si substrate and Al lines)
C. Esser, Infineon
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Introduction
1971
Intel anounces the i4004 microprocessor "a new era of integrated electronics" 2250 transistors, 10m technology, 108kHz
http://www.intel.com
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Introduction
1981 Intel i8088 29000 transistors, 3m technology, 8MHz invention of the PC (personal computer) IBM, A.Child, B.Gates
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Introduction
1965, Gordon E. Moore (co-founder Intel Corporation)
Electronics, Vol. 38(8)

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short this rate can be expected to continue, if not increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.
Prediction 1975: from 1980 on circuit density or capacity of semiconductor devices will double every two years instead of one year
http://www.pbs.org/transistor/
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Introduction
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Introduction
I think there is a world market for maybe five computers. Thomas Watson, Chairman of IBM, 1943 There is no reason for any individual to have a computer in their home. Ken Olson, President, Chairman and Founder of Digital Equipment Corp., 1977 640K ought to be enough for anybody. Bill Gates, Microsoft founder, 1981 (though today he denies he said it)
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Introduction
1958
1 transistor = 10 US$; first integrated circuit with 4 transistors: 150 US$ market 218106 US$ for 10 US$, you receive 50106 transistors (with passive components, interconnects, ...) market 150109 US$ unprecedented in industry's history
2000
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Introduction
state-of-the-art today
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Introduction
going really nano, i.e. <100nm ? top-down approach: extend current techniques to smaller sizes (EUV-L, x-ray lithography., nano-imprint, flip-up principle, i.e.: horizontal/vertical exchange, etc) problem: precision, costs bottom-up approach: start from individual atoms/molecules use principles of self-organization (self-assembly; inspiration from biology, biochemistry, chemistry) problem: long-range order difficult to achieve in practice: combination of both routes
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Outline
Introduction: overview, state of the art, semiconductor physics reminder
( condensed matter course)
Fabrication basics IC fabrication overview clean-rooms Silicon: from sand to wafer material deposition techniques lithography etching examples of devices: MEMS, NEMS Outlook: new and future techniques
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Semiconductors physics reminder
Energy gaps Si ~ 1.12 eV Ge ~ 0.66 eV GaAs ~ 1.43 eV

NB: kT (RT) ~25meV
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Si atoms intrinsic
As doped Si n-type other donors: P, Sb
Ga doped Si p-type other acceptors: B, Al
e.g.: resistivity changes by > 6 orders of mag. with a 1ppm B doping

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Basic (active) element of ICs FET (field-effect transistor)
voltage applied to capacitively coupled electrode (GATE) creates an electric field altering the nb of charge carriers in a semiconductor, thus modulating its conductivity (transfer resistor)
technologies for gate electrode pn-junction (junction FET or J-FET) Schottky barrier (metal-silicon FET or MESFET) insulated gate FET, like metal-oxide-semiconductor MOSFET
bipolar transistor: npn (or pnp), not capacitive
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Current vs voltage: diode behavior
depletion region shrinks
pn-junction
Reverse biased applied voltage enhances the internal potential difference
Forward biased applied voltage opposed to internal potential difference
breakdown
Ref. 3
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npn-transistor 2 diodes back-to-back
n-type p-type n-type
Ref. 3
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MESFET technology
Structure and sign convention of a metalsemiconductor junction
metal-semiconductor junction: barrier for electrons and holes

if the Fermi energy of the metal is somewhere between the conduction and valence band edge
Course Van Zeghbroeck
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Energy band diagram of the metal and the semiconductor
before contact
after contact
thermal equilibrium (Fermi levels adjusted)
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Workfunction of selected metals and their measured barrier height (eV) on germanium, silicon and gallium arsenide.
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MOSFET technology: MOS capacitor
energy band diagram Al/SiO2/p-Si
Metal (gate) : Oxide : Semiconductor : doping orientation typ.
Al (Mo, W, Cu), Poly-Si SiO2, d 1.7-10 nm p- or n-type silicon 1013 - 1018 cm-3 <100>
Ref. 3
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MOS capacitor
Assumptions for the ideal MOS structure: 1. No workfunction difference between metal and semiconductor 2. charges at any bias exist only in the semiconductor and on the metal surface 3. no carrier transport through the oxide under dc-biasing conditions i.e. Flat band condition at VGB=0
B. Fste, Infineon
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Real MOS structure: flatband voltage <> 0 VFB=MS
B. Fste, Infineon
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MOS capacitor
p-type semiconductor
B. Fste, Infineon
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MOS capacitor
B. Fste, Infineon
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MOS capacitor
B. Fste, Infineon
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MOS capacitor
B. Fste, Infineon
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MOS capacitor
B. Fste, Infineon
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MOS capacitor
B. Fste, Infineon
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MOSFET
B. Fste, Infineon
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B. Fste, Infineon
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MOSFET (n-channel) depletion type (on by default)
Vg=0
Vg<>0
enhancement type (off by default)
B. Fste, Infineon
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n-channel (NMOS) (charge carriers: electrons)
p-channel (PMOS) (charge carriers: holes)
Ref. 1
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Refs. 1 & 3
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CMOS: complementary MOS, todays most common technology n-channel MOS device in series with p-channel MOS device (when NMOS on, PMOS off and vice-vers, hence complementary ) simple design draws very little current (except when switched) low-power technology
basic logic gate: inverter Vin high (1): NMOS on, PMOS off, Vout=Vss (low, 0) Vin low (0): NMOS off, PMOS on, Vout=Vdd (high, 1)
B. Fste, Infineon
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CMOS: state-of-the-art
SOI substrate, Cu/low-k interconnection, 5 metal layers, features <0.13m, 300mm wafers (12 ")
Refs 1 & 3
thin Si oxide layers
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yet The simplest cell, a single bacterial cell from human gut perhaps, or a cell torn off the skin by rubbing it, is more complex than any machine yet built by people. Maddox, 1998
Refs 2
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Outline
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IC fabrication
example of (simple) CMOS process sequence
H. Xiao, Ref.1
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IC fabrication
H. Xiao, Ref.1
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IC fabrication
Ref. 3
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e.g.: wire bonding, packaging
NB: flip-chip packaging

H. Xiao, Ref.1
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Outline
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Clean room
importance of yield in industrial processes clean rooms
limit contaminants (air, people, facility, equipment, process (gas, chemicals, ...), static charges, .) special furniture and tools (paper, pens, ...)
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Clean room
clean room classes
class 1 less than 1 particle of diameter larger than 0.5m in a cubic foot clean house, typ. > 500000 particles per cubic foot
(Federal Standard 209E)

H. Xiao, Ref.1
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Clean room
clean room design
H. Xiao, Ref.1
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Clean room
simpler clean room design
H. Xiao, Ref.1
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Outline
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Silicon: from sand to wafer

14 +IV (+II)
[Ne]3s23p2 28.085g/mol 1410C 2.33kg/m3
Silicon
Si
2nd (after oxygen) most abundant in earths crusts: 26% 7th most abundant element in universe
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Si: SiO2 SiC Si nonmetallic element, indirect semiconductor glass (amorphous), quartz (cristalline) very hard (polishing) crystalline (semiconductor industry) typical resistivity: 100 m cm structure: cfc (diamond-like)
C. Heedt, Wacker Siltronic

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advantadges of Si over other semiconductors (Ge) cheap, abundant oxide (SiO2) strong and stable dielectric; grown easily by thermal oxidation larger band gap (1.1 eV): higher operation T larger breakdown voltage Doping elements n-type: P (phophorus), As (arsenic), Sb (antimony) p-type: B (boron)
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Si purification: natural Si oxide MGS EGS
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Si purification: MGS EGS
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EGS single cristal ingot: CZ growth (Czochralski method)
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Si ingot
up to 300mm diameter (FZ or floating zone purer butlimited to 200mm)
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Surface grinding
mark crist. orient.
flat: up to 150mm notch: > 200mm
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wafer sawing
edge rounding
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wafer finishing lapping (global planarization, double-sided) wet etching , isotropic (4:1:3 mixture of HNO3, HF and CH3COOH) CMP (chemical mechanical polishing) wet cleaning (RCA1, RCA2) surface roughness after the various treatment
Ref. 1
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Outline
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Fabrication: material deposition techniques

Physical processes Physical Vapor Deposition (PVD): thermal evaporation molecular beam epitaxy (MBE) pulsed laser deposition (PLD) sputtering Casting Chemical processes Chemical Vapor Deposition (CVD) Electrodeposition Langmuir-Blodgett films (LB)
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Fabrication: physical deposition techniques

film deposition basics: gas kinetics (mean free path: small holes filling, residual gas atoms: purity) UHV (p<10-9 mbar) necessary depending on final purity needed phase diagrams of materials to deposit (vacuum, temperature) control type of growth: homoepitaxy; heteroepitaxy; growth of polycristalline or amorphous layers; importance of strain misfit dislocations
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thin film growth mechanisms: heteroepitaxy (lattice match and surface energy differences)
Volmer-Weber (island growth):
Frank-Van der Merwe (layer growth; ideal epitaxy)
Stranski-Krastanov (layers + islands)
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thermal evaporation
resistance heated evaporation sources
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thermal evaporation e-beam evaporation effusion (Knudsen) cell
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Molecular Beam Epitaxy (MBE)
Ref. 3 & J.Faist
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Molecular Beam Epitaxy (MBE)
TEM pictures of a QCL GaAs/AlGaAs structure (J. Faist, Neuchtel)

J.Faist, Uni Neuchtel
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Pulsed Laser Deposition, laser ablation process (PLD)
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DC sputtering few 100V plasma p~10-1 - 10-3mbar sputtering of target by ions (typ. Ar) stoichiometry of target (~) preserved increase ionization rate of plasma with B-field: magnetron sputtering insulating targets: RFsputtering
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Casting (spinning) (typ. polymers, e.g. photoresists, polyimide)
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Fabrication: material deposition techniques

Physical processes Physical Vapor Deposition (PVD): thermal evaporation molecular beam epitaxy (MBE) pulsed laser deposition (PLD) sputtering Casting Chemical processes Chemical Vapor Deposition (CVD) Electrodeposition Langmuir-Blodgett films (LB)
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Fabrication: chemical deposition techniques

CVD: multiple wafer reactor e.g.: deposition of poly Si SiH4 SiO2 3 SiH4 + O2
Si + 2 H2 SiO2 + 2 H2
580-650C, 1mbar 450C
PECVD: plasma enhanced CVD, allows temperature reduction MOCVD: metal-organic CVD, use organometallic precursors (NB: thermal oxidation)
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CVD example: carbon nanotubes growth
(CH4, C2H4, C2H2...)
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CVD example: CNTs

hydrcarbon gases: carrier gases: temperature: catalyst: C2H2 (acetylene), C2H4 (ethylene), CH4 (methane) (+ ) H2, Ar 600-1000C Fe (Ni, Co)
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1m
SWNTs Fe, ethylene, 900C-1000C see e.g.: Dai et al. and Hafner et al.
~2nm
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lithographically patterned Fe film, acetylene, 600C-700C
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120
Length (m)
100 80 60 40 20 0 0 5 10 15
length of tubes vs time, flow and thickness SEM image perp. to SiO2/Si surface
Growth Time [min]

120
Length (m)
100 80 60 0 5 10 15 20
C2H2 Flow [sccm]

120
Length (m)
100 80 60 40 20 0 5 10 15 20
Z. Liu et al., 2002
Fe thickness [nm]
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Electrodeposition (electroplating)
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Langmuir-Blodgett (LB) technique
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Outline
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Different types of lithography
radiation
source
DLW
illumination control system
resist coated sample
Ref. 3
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Optical lithography
source wavelengths: optical: > 450nm UV: 365nm-435nm DUV: EUV: x-ray: 157nm-250nm 11nm-14nm < 10nm
Ref. 3
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Optical lithography
masking methods
contact MFS=(d.)1/2 proximity poorer resolution projection better resolution
(diffrac. limited, adj. Rayleigh crit.)
MFS ~ [(d.+g)]1/2 mask suffers
reduction possible (decreases errors) stepper (multiple exp.)
Ref. 3
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Optical lithography
phase-shifting technique
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Optical lithography
photoresists positive made soluble upon exposure (chain scission) e.g. PMMA (DUV, e-beam), DQN negative initiates cross-linking of side chains or polymerization of mono/oligomeric species e.g. maN400
Ref. 3
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Optical lithography
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Optical lithography
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Optical lithography
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Optical lithography
photoresists profiles
Ref. 2
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Optical lithography
some important points resist baking: soft-bake, PEB, hard bake (NB: Tg polymer) adhesion layer (HMDS) development times/temperatures fresh products DOF (depth of focus) DOF /(NA)2
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EUV lithography (R&D)

reflection optics (10-15nm: no transparent enough materials for lenses)
Ref. 3
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x-ray lithography (R&D)

i.e: same problem as EUV: no lenses neither mirrors (why ?) proximity x-rax lithography (PXL) only, resolution limit, ~30nm complex (multilayer) masks, DUV resists ok
also LIGA (lithographie, galvanoformung, developped IBM, 1975) x-ray used for high-aspect ratio structures, masters fabrication for further plastic replication
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electron beam lithography (EBL)

precise (energy, dose) relatively slow (industrial application: parallel beams) resolution limit ~ 10nm (50nm) no mask large DOF large scattering of electrons
Refs. 1 & 3
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Emerging lithography technologies

STM lithography: low energy e- (<50eV), resolution down to 50nm, short mfp (2nm) thin resist layer e.g. SAM
Sugimura et al., J. Vac. Sci Technol. (1999)
2nm 20nm a-Si etch (etch stop)
min-electro chemical cell (H2O vapor)
HF etch (oxide)
Ref. 2
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soft lithography: microcontact printing (MCP)
PDMS, e.g Sylgard 184, DOW Corning
B. Michel et al., Advanced Semiconductor Lithography, 2001
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master
first used to print alkanethiols on gold surfaces quick and cheap method to perform simple assays (e.g.: immunoassay: crossed stamped lines)
stamp
printed and etched pattern
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Outline
Introduction: overview, state of the art, semiconductor physics reminder Fabrication basics IC fabrication overview clean-rooms Silicon: from powder to wafer material deposition techniques lithography etching examples of devices: MEMS, NEMS Outlook: new and future techniques
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Fabrication: etching
Chemical: wet etching (can be anisotropic due to crystal-face selectivity) Physical etching (sputtering) ion milling, FIB (focused ion beam) dry etching (plasma assisted techniques, pressures up to 10mbar) (more a combination of physical and chemical material removal) key points: etch rates, selectivity
also CMP: chemical mechanical polishing to achieve global planarization combine mechanical abrasion with chemical etching key parameters: force, slurry type, pad velocity
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Fabrication: wet etching

use chemical solutions to dissolve material 3 steps: reactive species to surface/ etch products / rinse, dry isotropic
anisotropic
http://www.memsguide.com
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SiO2 6:1 buffered in NH4F or 10:1 and 100:1 HF in H2O (NB: 1:1 HF (49% HF in H2O) too fast) SiO2 + 6 HF H2SiF6 + 2 H2O Si (H2SiF6 soluble in H2O)
polycrystalline or single-crystal isotropic: mix of HNO3 and HF (cyclic process: HNO3 oxidizes Si, HF removes oxide) Si + HNO3 + 6 HF H2SiF6 + HNO2 + H2O + H2 anisotropic (cystalline Si): (100) rate / (111) rate ~ 100 at 80C KOH 23.4% wt, C3H8O 13.3% wt (isopropyl alcohol), H2O 63.3% wt yields V-shaped groove
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Si3N4 H3PO4 91.5% concentration at 180C (etch rate ~ 100/min) Si3N4 + 4 H3PO4 Si3(PO4)4 + 4 NH3 silicon phosphate (Si3(PO4)4) and amonia (NH3) are water soluble selectivity to thermally grown SiO2 Si metals Al Ti
> 10:1 > 33:1
mix of acids (phosphoric, acetic, nitric) and water mix of sulfuric acid and hydrogen peroxide
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Fabrication: dry etching

RIE: reactive ion etching
both physical and chemical
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Fabrication: dry etching
DRIE (key process for MEMS) ICP RIE SF6 alternated with C4F8 (to passivate walls), Bosch process selectivity Si:SiO2, 150:1 profile angle +/- 1
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Outline
Introduction: overview, state of the art, semiconductor physics reminder Fabrication basics IC fabrication overview clean-rooms Silicon: from powder to wafer material deposition techniques lithography etching examples of devices Outlook: new and future techniques
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MEMS/NEMS and devices

from MEMS (micro-electromechanical systems) e.g. Si gears for watch industry: lower friction and inertia
CSEM & Ulysse-Nardin
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electrostatic micromotor fabricated from silicon
individual mechanical micromirrors part of a Texas Instruments Digital Light Processor (MOEMS)
Physics World, Feb. 2001
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fabrication process reminder
structural layer
sacrificial layer
substrate
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ion-selective electrode array platform for in-vitro intracellular recording
O. Guenat,et al., Microfabrication and characterization of an ion-selective microelectrode array platform, Sensors & Actuators, B, 2003.
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down to NEMS
masses in 10-15g to 10-18 g range ( L3) resonators above 10GHz ( 1/L) (f ~ (spring cst/eff. mass)1/2, spring constant L) very low power: 10-18W threshold (thermal fluc. at 300K) low dissipation, high Q factor: sensitive to damping sensors (sensitivity potentially reaching quantum limit)
NB: 10x10x100 nm Si beam contains ~ 5 x 105 atoms, among which ~3 x 104 reside at the surface (i.e.: > 10% of the constituents are surface or near-surface atoms)
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nano-tweezers: electrostatic actuation actuation amplitude down to 6 pm (rms)/ sqrt(Hz)
Ch. Meyer, H. Lorenz, and K. Karrai, "Optical detection of quasi-static actuation of nanoelectromechanical systems" Appl. Phys. Lett. 83, 2420 (2003).
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Nanomechanical Electron Transport: quantum-bell: max current at fdrive~ resonance freq.
avg nb of e- shuttled per cycle
A Erbe, Ch Weiss, W Zwerger, and R H Blick, Phys. Rev. Lett. 87, 096106 (2001) M Jonson and R Shekhter, Phys. World 16, 21 (2003).
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Integration: hybrid devices
Tech. Roadmap for Nanoelectronics, IST program, European Commission
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END
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Sources and ressources

Books Introduction to Semiconductor Manufacturing Technology H. Xiao, Prentice-Hall, 2001. Fundamentals of Microfabrication: The Science of Miniaturization M. Madou, 2nd ed., CRC Press, 2002 Nanoelectronics and Information Technology R. Waser ed., Wiley-VCH, 2003 VLSI Technology (more physical) SM. Sze, 2nd ed., McGraw-Hill, 1988 cd-rom: DVD: 4th Dresdner Sommerschule Mikroelektonik, 2003. www.sommerschule-mikroelektronik.de EPFL CMI
web sites www.memsnet.org; www.biomems.net http://mmadou.eng.uci.edu/LivingBook/webterlist.htm Semiconductor physics http://ece-www.colorado.edu/~bart/book/contents.htm www.techlearner.com/semiconductors.htm web sites from companies: Intel, Infineon, IBM
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Introduction
The Lives and Death of Moore's Law by Ilkka Tuomi First Monday, volume 7, number 11 (November 2002), URL: http://firstmonday.org/issues/issue7_11/tuomi/index.html
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http://www.vcs.ethz.ch/chemglobe http://chemlab.pc.maricopa.edu/periodic
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Schedule: 1st hour: slides 1-26 2nd hour: slides 26-62 3rd hour: slides 62-82 4th hour: slides 82-94 5th hour: slides 94-116
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NANO III

Chapter: Micro- and nano-fabrication

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1958 Jack Kilby, Texas Instruments first IC (Integrated Circuit)

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1965, Gordon E. Moore (co-founder Intel Corporation)

Electronics, Vol. 38(8)

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Semiconductors physics reminder

Energy gaps Si ~ 1.12 eV Ge ~ 0.66 eV GaAs ~ 1.43 eV

Semiconductors physics reminder

As doped Si n-type other donors: P, Sb

Ga doped Si p-type other acceptors: B, Al

e.g.: resistivity changes by > 6 orders of mag. with a 1ppm B doping

Semiconductors physics reminder

bipolar transistor: npn (or pnp), not capacitive

MC, Nano III, 24.04.04, 18

Semiconductors physics reminder

Reverse biased applied voltage enhances the internal potential difference

Forward biased applied voltage opposed to internal potential difference

MC, Nano III, 24.04.04, 19

Semiconductors physics reminder

npn-transistor 2 diodes back-to-back

n-type p-type n-type

MC, Nano III, 24.04.04, 20

Semiconductors physics reminder

Structure and sign convention of a metalsemiconductor junction

metal-semiconductor junction: barrier for electrons and holes

Course Van Zeghbroeck

MC, Nano III, 24.04.04, 21

Semiconductors physics reminder

thermal equilibrium (Fermi levels adjusted)

Course Van Zeghbroeck

MC, Nano III, 24.04.04, 22

Semiconductors physics reminder

Course Van Zeghbroeck

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Semiconductors physics reminder

Metal (gate) : Oxide : Semiconductor : doping orientation typ.

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Semiconductors physics reminder

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Semiconductors physics reminder

Real MOS structure: flatband voltage <> 0 VFB=MS

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Semiconductors physics reminder

MC, Nano III, 24.04.04, 27

Semiconductors physics reminder

MC, Nano III, 24.04.04, 28

Semiconductors physics reminder

MC, Nano III, 24.04.04, 29

Semiconductors physics reminder

MC, Nano III, 24.04.04, 30

Semiconductors physics reminder

MC, Nano III, 24.04.04, 31

Semiconductors physics reminder