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RISC? RISC, or Reduced Instruction Set Computer.

is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

Certain design features have been characteristic of most RISC processors:

one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called <i.pipelining< i="">; </i.pipelining<>

pipelining: a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory

MIPS Architecture The Stanford research group had a strong background in compilers, which led them to develop a processor whose architecture would represent the lowering of the compiler to the hardware level, as opposed to the raising of hardware to the software level, which had been a long running design philosophy in the hardware industry. Thus, the MIPS processor implemented a smaller, simpler instruction set. Each of the instructions included in the chip design ran in a single clock cycle. The processor used a technique called pipelining to more efficiently process instructions. MIPS used 32 registers, each 32 bits wide (a bit pattern of this size is referred to as aword). Instruction Set The MIPS instruction set consists of about 111 total instructions, each represented in 32 bits. An example of a MIPS instruction is below:

add $r12, $r7, $r8

Above is the assembly (left) and binary (right) representation of a MIPS addition instruction. The instruction tells the processor to compute the sum of the values in registers 7 and 8 and store the result in register 12. The dollar signs are used to indicate an operation on a register. The colored binary representation on the right illustrates the 6 fields of a MIPS instruction. The processor identifies the type of instruction by the binary digits in the first and last fields. In this case, the processor recogizes that this instruction is an addition from the zero in its first field and the 20 in its last field.

The operands are represented in the blue and yellow fields, and the desired result location is presented in the fourth (purple) field. The orange field represents the shift amount, something that is not used in an addition operation. The instruction set consists of a variety of basic instructions, including: 21 arithmetic instructions (+, -, *, /, %) 8 logic instructions (&, |, ~) 8 bit manipulation instructions 12 comparison instructions (>, <, =, >=, <=, ) 25 branch/jump instructions 15 load instructions 10 store instructions 8 move instructions 4 miscellaneous instructions

How Pipelining Works PIpelining, a standard feature in RISC processors, is much like an assembly line. Because the processor works on different steps of the instruction at the same time, more instructions can be executed in a shorter period of time. A useful method of demonstrating this is the laundry analogy. Let's say that there are four loads of dirty laundry that need to be washed, dried, and folded. We could put the the first load in the washer for 30 minutes, dry it for 40 minutes, and then take 20 minutes to fold the clothes. Then pick up the second load and wash, dry, and fold, and repeat for the third and fourth loads. Supposing we started at 6 PM and worked as efficiently as possible, we would still be doing laundry until midnight.

However, a smarter approach to the problem would be to put the second load of dirty laundry into the washer after the first was already clean and whirling happily in the dryer. Then, while the first load was being folded, the second load would dry, and a third load could be added to the pipeline of laundry. Using this method, the laundry would be finished by 9:30.

RISC Pipelines A RISC processor pipeline operates in much the same way, although the stages in the pipeline are different. While different processors have different numbers of steps, they are basically variations of these five, used in the MIPS R3000 processor: 1. 2. 3. 4. 5. fetch instructions from memory read registers and decode the instruction execute the instruction or calculate an address access an operand in data memory write the result into a register

Pipelining Developments In order to make processors even faster, various methods of optimizing pipelines have been devised. Superpipelining refers to dividing the pipeline into more steps. The more pipe stages there are, the faster the pipeline is because each stage is then shorter. Ideally, a pipeline with five stages should be five times faster than a non-pipelined processor (or rather, a pipeline with one stage). The instructions are executed at the speed at which each stage is completed, and each stage takes one fifth of the amount of time that the non-pipelined

instruction takes. Thus, a processor with an 8-step pipeline (the MIPS R4000) will be even faster than its 5-step counterpart. The MIPS R4000 chops its pipeline into more pieces by dividing some steps into two. Instruction fetching, for example, is now done in two stages rather than one. The stages are as shown: 1. 2. 3. 4. 5. 6. 7. 8. Instruction Fetch (First Half) Instruction Fetch (Second Half) Register Fetch Instruction Execute Data Cache Access (First Half) Data Cache Access (Second Half) Tag Check Write Back

Dynamic pipelines have the capability to schedule around stalls. A dynamic pipeline is divided into three units: the instruction fetch and decode unit, five to ten execute or functional units, and a commit unit. Each execute unit has reservation stations, which act as buffers and hold the operands and operations.

While the functional units have the freedom to execute out of order, the instruction fetch/decode and commit units must operate in-order to maintain simple pipeline behavior. When the instruction is executed and the result is

calculated, the commit unit decides when it is safe to store the result. If a stall occurs, the processor can schedule other instructions to be executed until the stall is resolved. This, coupled with the efficiency of multiple units executing instructions simultaneously, makes a dynamic pipeline an attractive alternative.

The Overall RISC Advantage Today, the Intel x86 is arguable the only chip which retains CISC architecture. This is primarily due to advancements in other areas of computer technology. The price of RAM has decreased dramatically. In 1977, 1MB of DRAM cost about $5,000. By 1994, the same amount of memory cost only $6 (when adjusted for inflation). Compiler technology has also become more sophisticated, so that the RISC use of RAM and emphasis on software has become ideal.

Reduced Instruction Set Computers (RISC) - 1980s + Minimal instruction set all instructions use simple addressing modes to reduce decoding difficulty most instructions require one clock tick to execute (simplifies pipelining) Why? More chip space is devoted to making the most common instructions as fast as possible. Some less common instructions may be slower, but overall performance is increased. Compilers have improved to the point that well-optimized sequences of simple (very fast) commands often outperform the more complicated multi-cycle instructions. RISC designs could fit on a single chip, which reduced cost, increased reliability, and increased clock speeds! Performance/Costs Larger code footprints, more/larger instructions that CISC. Initially RISC ISA could not include support for floating point instructions. They had to be performed in software and were very slow. As chip densities increased floating point instructions were added to the RISC

CHARACTERISTICS:
RISC is a design philosophy (Fast is good!) Common RISC features: Instruction pipelining Uniform instruction length This assumption simplifies instruction fetch, decode, and pipeline design Delayed branching

Branches are not decided until the execute phase anything in the pipeline after the branch may have to be annulled if the next address is incorrect. A branch occurs every five to ten instructions in many programs. If we executed a branch every fifth instruction and only half of our branches fell through, the lost efficiency due to restarting the pipeline after the branches would be 20%! Increased pipeline efficiency by requiring an instruction in the branch delay slot (which may be a No-Op). Instruction in the branch delay slot is executed regardless of the branch decision. Branch prediction and the ability to annul instructions in the pipeline has greatly increased the efficiency of branches.CEG 360/560 - EE 451/651 Section IV 46

Load/Store architecture

The only memory access allowed are Load and Store! All other operations are register-register. Otherwise it would be very difficult to have uniform length instructions Instructions that did both a memory fetch and a operation would require two execution stages, one to calculate the address, and one to perform the operation. This way, each instruction has exactly one executionstage. Load/Stores can take more time than other instructions, if we are careful to load registers well before we need them, we can often reorder instructions so that the pipeline is always full. Simple addressing modes Necessary to reduce the ISA and allow uniform instruction lengths. Some memory references may take more real instructions than they might have taken on a CISC machine, and be more difficult for a human to understand, but because everything executes more quickly, it is generally still a performance win

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