The total memory of an 8051 system is logically divided into program memory and data memory.

Program memory stores the program to be executed while data memory stores data like immediate results, variables, and constants required for execution of the program. Program memory is invariably implemented using EPROM, because it stores only program code which is to be executed thus it need not be written into. However the data memory may be read from or written into, thus implemented using RAM. Further the program memory and data memory both may be categorized as on-chip (internal) and external memory, depending on whether the memory is physically exists on chip or it is externally interfaced. 8051 can (address support) 4kB on chip program memory whose map starts from 0000 H to 0FFF H. It can address 64kB of external program memory under the control of PSEN signal, whose address map is from 0000 H to FFFF H. Here the map of internal program memory and external program memory may overlap. However, these two memory spaces can be distinguished by PSEN signal.

MEMORY AND IO ADDRESSING

8051 supports 64 kB of external data memory whose map starts at 0000 H and ends at FFFF H. This external data memory can be accessed under the control of register DPTR which stores he addresses of external data memory accesses. 8051 generators RD and WR signals during external memory accesses. The chip select line of external data memory may be derived from the address lines. Internal data memory 8051 consists of two parts: (1) RAM block of 128 bytes (256 bytes in some various of 8051). (2) Is a set of addresses from 80 H to FF H which includes addresses allotted to the special function register. The address map of 8051 internal 128 bytes RAM starts from 00 to 7F H. This RAM can be addressed by using direct or indirect addressing modes. However the special function register address map i.e., from 80 H to FF H is accessed only with direct addressing mode. In case of 8051 versions with 256 bytes on-chip RAM, the map starts from 00 H tan FF H. In this case it may be noted that the address map of special function register i.e., 80 H to FF overlaps with upper 128 bytes of RAM. The way of addressing i.e., addressing mode is differentiates between these two memory spaces. The upper 128 bytes of 256 byte on-chip RAM can be accessed only using indirect addressing; while the lower 128 bytes can be accessed using either direct or indirect addressing. The SFR can be accessed only by using direct addressing.

The lower 128 bytes of RAM whose address map is from 00 to 7F is functionally organized in 3 sections. The address block from 00 to 1F i.e., the lowest 32 bytes from the 1st section, is divided into 4 banks of 8 register denoted as 00, 01, 10 and 11. Each of these banks contain 8. 8-bit register. The stack pointer gets initialized at address 0.7 H i.e., the last address of bank 00, after reset operation.

After reset bank 0 is selected by default but the actual stack data is stored from 08 H onwards; i.e., bank 01, 10 and 11. Note that 20 is the address of the 1st byes of the on-chip RAM. The 3rd block of internal memory occupies addresses from 30 H to 7F H. This block of memory is byte addressable memory space. After reset bank 0 is selected by default but the actual stack data is stored from 08 H onwards; i.e., bank 01, 10 and 11. Note that 20 is the address of the 1st byes of the on-chip RAM. The 3rd block of internal memory occupies addresses from 30 H to 7F H. This block of memory is byte addressable memory space.