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Introduction
Introduction, Design Example and Manual Conventions
Verilog or VHDL Constraints Simulation Synthesis Libraries
This sections describes what the manual is about. It outlines the design methodology used, and gives a description of the design example used in the tutorial. The convetions used in the manual are also described.
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Specications VHDL or Verilog Behavioral Simulation Synthesis & Test Gate-Level Simulation
SYNOPSYS CADENCE
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ACI 3 CLK RST
ACO 3
VHDL (test.vhd)
entity test is port ( RST, CLK: in std_logic; ACI: in std_logic_vector(2 downto 0); ACO: out std_logic_vector(2 downto 0); end alu; architecture behav of test is signal ACC: std_logic_vector(2 downto 0); ACC_PROC: process (RST, CLK, ACI, ACC) begin if (RST = 1) then ACC <= (others => 0); elsif (CLKevent and CLK = 1) then ACC <= ACC + ACI; end if; end process ACC_PROC; ACO <= ACC; end A;
Verilog (test.v)
module test (RST, CLK, ACI, ACO); input RST, CLK; input [2:0] ACI; output [2:0] ACO; reg [2:0] ACO; always @(posedge CLK or posedge RST) begin if (RST) ACO = 0; else ACO = ACO + ACI; end endmodule
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Setup the Design Environment
Synthesis and Simulation Setup Files
target_library = {kcells.db pads.db} link_library = {. kcells.db pads.db} symbol_library = {kcells.sdb} edifout_netlist_only = true
In this step you setup the synthesis and simulation design environment by using the Synopsys setup les. Some of the variables that need to be specied before you can run synthesis and gate-level simulation include the technology and symbol libraries of the target technology, gate-level simulation libraries, as well as the search path to these and other libraries and design references.
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Go to your design directory cd design_dir Copy the sample synthesis le from the directory containing the technology design kit for Synopsys. cp /CMC/kits/technology/synopsys/technology.version/dotles/dc_dot_le .synopsys_dc.setup
TUTORIAL STEP
design_dir Your design directory technology The name of the technology you are targeting. Examples are bicmos, mitel15, and cmosis5. version The version of the technology CMC design kit for Synopsys. Examples are 1.1 and 2.1 dc_dot_le The name of the sample synthesis setup le. In some technologies this sample le is given the name .synopsys_dc.setup (i.e. it is a hidden le and hence you have to list all dot les in order to check if it exist - use the Unix command ls .synopsys_*), while in others, the name is usually target_lib.synopsys_dc.setup, where target_lib is the name of the target library in the technology, e.g. kcells in the bicmos technology.
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search_path This species the directories to be searched by the synthesis tools for les. It should include at least the following:
search_path = {. design_kit_dir//syn synopsys_dir/libraries/syn}
TUTORIAL STEP
where . indicates the directory you started the synthesis tools from (your design directory) target_library Species a list of technology libraries of components used when compiling a design.
example: target_library = {hcells.db}
company = put_your_company_name_here designer = put_your_name_here search_path = {. /CMC/kits/cmosis5/synopsys/ cmosis5.1.1/3.4b/syn /CMC/tools/synopsys.3.4b/ libraries/syn} target_library = {hcells.db} link_library = {* hcells.db} symbol_library = {hcells.sdb}
link_library Species a list of design les and libraries used during linking. Linking resolves design references by connecting the design to all library components and designs it references. For this reason include an asterisk (*) in the list to include all the designs in your design library.
example: link_library = {* hcells.db}
symbol_library Species the libraries that contain the graphical information of symbols of components used when displaying the schematic of a compiled design. Files for symbol libraries usually end in .sdb extension.
example: target_library = {hcells.sdb}
designer Your name (the designer). This is displayed on the design schematics.
example: designer = Peter Nyasulu
company The companys name where the Synopsys tools are installed. It is also displayed on design schematics.
example: company = Carleton University
design_kit_dir The directory containing the technology design kit for Synopsys. Normally it should be /CMC/kits/technology/synopsys/technology.version, where technology is the name of the technology (e.g mitel15, bicmos, cmosis5) and version is the kit version (e.g. 1.1) synopsys_dir The Synopsys tools root directory. Normally it should be /CMC/tools/synopsys.3.4b.
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Go to your design directory cd design_dir Using your favorite editor, open/create the le .synopsys_vss.setup. For example, if you are using emacs editor, type the following at the Unix prompt: emacs .synopsys_vss.setup & In the le, specify the following variables: FTGS Library This denes the names of the libraries to be used in the RTL le for gate-level simulation, as well as the path to the actual FTGS libraries (the dened library name doesnt have to be the same as the actual name of the library). You must dene this for each of the target library used in your design (libraries specied in the target_library variable in .synopsys_dc.setup le). Syntax: gate_library: /CMC/kits/technology/synopsys/ technology.version/sim/target_library_name Example (when using the cmosis5 technology): hcells: /CMC/kits/cmosis5/synopsys/cmosis5.1.1// 3.4b/sim/hcells Simulation Time Base/Resolution The units and resolution of the simulation times. For example, to set simulation units to nanoseconds, and the resolution to 100 picoseconds, add the following lines in the setup le: TIME BASE = NS TIME_RES_FACTOR = 0.1 Editor Editor that synopsys invokes when you execute any of the Synopsys environment edit le commands. The default editor is set to vi. For example, to set the editor to Emacs, include the following line in the setup le (assuming emacs is the command that is used to invoke the Emacs editor): EDITCMD = emacs
TUTORIAL STEP
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Simulate the Verilog RTL Model
Verify the Functionality of the RTL Model
always @(posedge clk) begin c = a & b; end clk b o
In this step you verify the functionality of the Verilog behavioral model by simulating it using Cadence Verilog-XL Simulator. You can print the results of the simulation (in text format) using the in-built Verilog system tasks, or you can view the signals waveforms using Cadence Cwaves waveform viewer.
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initial begin $shm_open (database_directory) $shm_probe (var1, var2, ..., varn) end where, database_directory The name of the directory where the waveforms data should be stored. Enclose the name in double quotation marks. var1, var2, ..., varn The list of Verilog variables whose waveforms should be evaluated and stored. You can then later choose which of these waveforms you display in the waveform viewer. Note that any variable that is omitted from the probe list cannot be viewed in cwaves without having to re-run the whole simulation.
TUTORIAL STEP
initial begin $shm_open (shm_waves) $shm_probe (RST, CLK, ACI, ACO) end
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To start the Cadence-XL simulator, at the Unix prompt, type: verilog design_tb.v design.v where, design_tb.v The name of the test bench Verilog source le. design.v The name of the design Verilog source le.
TUTORIAL STEP
To start the Cadence Cwaves waveform viewer, at the Unix prompt, type: cwaves &
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C Cadence Cwaves File Edit View Options Load Data... Plot... Save Setup... Restore Setup... Close Data Quit Help
1. Type in shm_dir
File Path: File Name: Server Host Name: OK Cancel Apply Help
2. Click
shm_waves shm_dir The name of the directory that was specied in the $shm_open task in the test bench. Note that this directory name is typed in the File Name eld, and not in the File Path eld. The default in the File Path eld is a dot (.), which means the directory where you started cwaves from. If this is not the directory where the shm_dir is, you must specify the full path of the directory in this eld. The default for the Server Host Name, which is usually localhost, should sufce.
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C Cadence Cwaves File Edit View Options Browser/Display Tool... Add Signal By Name... Cut Copy Paste Delete Strips Signals Markers Viewports Comments Logic Overlay Display Values... 1. Select design_tb Help
Mode:
Display
Help
Delete Group
design_tb
3. Select varn
4. Click
test_tb design_tb The module name of the test bench. Select it by leftclicking once on it. Once the test bench module name is selected, the subscope up/down buttons, which you are supposed to click in step 2, will be activated. RST, CLK, ACI, ACO var1, var2, ... The variables whose waveforms are to be displayed. Repeat steps 3 and 4 for each of the variable you want to display. Alternatively, you may select all the signals at once in step 3 by clicking on the rst variable, then hold down the shift button, and click on the last.
Signals
Delete Signals
5. Click
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Synthesize the RTL Model
From RTL to Schematic/Netlist
always @(posedge clk) begin c = a & b; end a b clk d q c
This step will convert the RTL model of your design into a netlist (and schematic) using the cells in the target technology library. The design is also optimized for timing and area. Synopsys power optimizations are only possible with ECL designs and hence are not covered in this manual.
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To start the Design Analyzer, type the following at the Unix prompt (The & starts the Design Analyzer in background so that you can use the Unix window for other commands): design_analyzer & Optionally, you can use the Design Compiler (dc) shell and run the synthesis using dc shell commands only. Since the dc shell is a text-based window, you will not be able to see the schematic. It is therefore not advisable to use the dc shell unless you are very experienced with it. To start the dc shell, type the following at the Unix prompt: dc_shell
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Defaults... Variables... License Execute Script... Scripts T Command Window...
design_analyzer>
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help
C Command Window
Errors, Warnings, & Reports Error: File hdl_le could not be found in the search path ... - make sure the search path includes the directory where the source les are. To include the directory where you start Design Analyzer from, include a dot (.) as one of the components of the search path. - Unlike other stand-alone VHDL/Verilog compilers, you must specify the extension of the le (if the le has an extension) even when a le has a standard VHDL/Verilog extension of .vhd, .vhdl or .v Error: Could not read the following target | link | symbol | synthentic library: ... - Check that the library you have specied in the .synopsys_dc_setup le or using the Setup Defaults... is existent and readable and has its path included in the search path. Error: Depending on 2 edges of same variable clock_pin not supported ... - You cannot use both the positive and negative edges of the same clock variable in the same process or always block.
test.v(test.vhd) hdl_le(s) A list of VHDL or Verilog les. Note that Design analyzer does not automatically append the standard VHDL/Veriolg extensions (.vhd, .vhdl, .v), and therefore the le must be specied with its extension if it has one. WORK library The library where the analyzed les should be put. Normally, select the WORK or DEFAULT library, which is usually mapped to the directory where your design source les are. format The format of the HDL le. It is either verilog or VHDL. CLK clock_pin A variable used as a clock in the VHDL or Verilog design.
4. Click
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Library: DW01 DW02 WORK Design: module1(verilog) module2(verilog) entity1(arch) antity2(arch) Parameters: Re-Analyze Out-OfDate Libraries OK Cancel 4. Click Help 1. Select library
C Command Window
Errors, Warnings, & Reports Error: Clock variable clock_pin is being used as data in ... - clock_pin, used as a clock with the statements clock_pinevent and clock_pin = 1 (= 0) or posedge (negedge) clock_pin, cannot be used in the right-hand side of an assignment statement in the same process or always block. Use a separate process or always block to make this assignment. Error: This use of clock edge specication not supported in ... - You cannot use both the positive and negative clock edges of the same clock variable in the same process or always block. - In VHDL, you cannot use more than one clock_pinevent and clock_pin = 1 (= 0) clock statements in one process. If possible, make all assignments in one clock statement or use more than one process. Info: Inferred memory devices in process ... Info: Inferred THREE-STATE control devices in process ... - Always check this information about inferred devices to make sure that your RTL description does not imply unnecessary ip-ops (due to variable assignments in clock_pinevent and clock_pin = 1 (= 0) statements or always blocks with posedge (negedge) clock_pin statements), latches (due to variables not assigned to in all conditions of if and case statements - to aviod latches, also make the variable assignment in the else or default clauses of these statements), and tristate buffers.
test entity The entity name of the VHDL model. If the design contains more than one entity, elaborate each entity separately. behav arch The architecture of the VDHL entity. test module The module name of the Verilog model. If the design contains more than one module, elaborate each module separately. WORK library The library where the les were analyzed into. Normally, select the WORK or DEFAULT library, which is usually mapped to the directory where your design source les are. CLK clock_pin A variable used as a clock in the VHDL or Verilog model.
3. Turn ON
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints O1 Optimization Directives O2 Clock Name: Clock Port: Specify... Skew... Help
C Command Window
2. Type period
3. Turn ON
4. Click
Clock Name: Clock Delay Type Ideal Rise: Propagated Uncertainity Min: Max: Fall: Same Rise and Fall
5. Click
6. Swith ON skew_type
7. Click
CLK clk_pin Pin or port on which clock constraints are to be set. 20 period The period of the clock. Only the number should be specied - the units (usually ns) are specied in the technology le. propagated skew_type Species the type of clock network. It is either ideal (an ideal clock network with no skew) or propagated (the clock skew depending on the propagation delays through the network). The default is ideal.
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives
T
C Command Window Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...
Design Name: Ungroup Boundary Optimization Sequential Elements: Port is Pad: Test Scan Style:
Structured Logic Apply Timing Driven Structuring Apply Boolean Optimization Apply Cancel
3. Click
full_scan test_methodology The test methodolgy to be used. It is either full_scan or partial_scan. The default is full_scan. multiplexed_ip_op scan_style Denes the scan-test implementation. It is either multiplexed_ip_op, lssd, aux_clock_lssd, clocked_scan, combinational or none. See Appendix A.1 for details.
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Flip Flop...
Flatten Logic Flatten Effort: Flatten Minimize: Flatten Phase: Low Medium High Single Output Multiple Output None Dont Apply Apply Strategy
2. Click
C Synopsys Design Analyzer Setup File Edit View Design Constraints... Timing Constraints... Derive... Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives Help
C Command Window
1. Type max_fanout
Design Name: Optimization Constraints: Max Area: Max Power: Design Rules: Max Fanout: Max Transition: Test Constraints: Min Fault Coverage: Area Critical Apply 4. Click 5. Click 95% Cancel
10 max_fanout The value of the maximum fanout. 2.0 max_trans The maximum transition time. Only the number should be specied, but its units must be consistent with those specied in the technology library (usually ns). test design Name of the design (entity name or module name)
2. Type max_trans
3. Turn ON
Timing Critical
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window
design_analyzer> 1. Turn ON Map Design Map Effort: 2. Turn ON map_effort Low Medium High
Low
Medium
High
3. Turn ON
4. Click
OK
medium map_effort Species how much effort and time should be spent by the processor on mapping. Valid settings are Low, Medium and High. High effort yields a better optimized circuit, but the CPU time taken to achieve this might be too much for very large designs. The default map effort is Medium.
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Link Design... Check Design... Time Design Show Timing... Show Net Load... Highlight Test Report... Report... Help
C Command Window
check_design
design_analyzer>
test design The name of the design you are currently checking. port_name The name of any port on your design.
1. Turn ON
3. Click
Warning: In design design port port_name is not connected to any nets. - Make sure that the port port_name is intentionally not associated with any logic in your HDL description. Otherwise if the port is included for future expansion of the design, or for component interface consistency, the warning may be ignored.
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
C Command Window
check_test
1. Turn ON test_methodology
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design_analyzer> Methodology: 2. Select scan_style Scan Style: Full Scan Partial Scan
3. Click
Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager...
4. Click
full_scan test_methodology The test methodolgy to be used. It is either full_scan or partial_scan. The default is full_scan. multiplexed_ip_op scan_style Denes the scan test implementation. It is either multiplexed_ip_op, lssd, aux_clock_lssd, clocked_scan, combinational or none. See Appendix A.1 for details..
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window
create_test_patterns
Errors, Warnings, & Reports Warning: Design has no scan path. Generated vectors will not be saved. - Ignore this warning. It simply reminds you that you have run ATPG before inserting scan test circuitry. ATPG will be run again later.
Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... 2. Click Test Manager... Format Vectors... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Display Reports... Cancel Verbose
5. Click
design.vdb Compact Patterns Efoort: Low (Backward) Contention Check Float Check Additional Options...
4. Click
3. Click
Background Cancel
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Link Design... Check Design... Time Design Show Timing... Show Net Load... Highlight Test Report... Report... Help
C Command Window
2. Turn ON
3. Turn ON
Report: In the contraints report, note the (MET) and (VIOLATED) against each of the design constraints set earlier. - This shows that the design constraint has either been met or violated by the indicated value. Report: In the timing report, note the slack (MET) at the end of the report. - This indicates the time that the longest path in the design settles before the clock changes. A negative value indicates a violation. Increase the clock period or reoptimize the design if there is a slack violation.
4. Click
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window
insert_test -no_disable
Errors, Warnings, & Reports Warning: Deleting current test program test_program_name because it is not consistent with the current design. - Again, ignore this warning. It refers to the ATPG that was run in step 6.11. Since the design has changed, the next ATPG will use a new initial fault list.
2. Turn OFF
3. Click
Background Cancel
test.vdb test_program The test program that was created with the last ATPG run and is currently being deleted.
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Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager... 1. Click Format Vectors... Display Reports... Cancel
4. Click Insert Scan Options: Insert Test Cells Route Scan Path Disable Internal Three-State Drivers
compile -incremental_mapping
Low
Medium
High
OK
3. Click
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OK
Cancel
Step 6.12 (Area and Timing Analysis) Errors, Warnings, & Reports
Low
Medium
High
C Command Window
Full Scan
Partial Scan
Contains Existing Scan Circuitry Check Design Rules 1. Turn ON Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager... Format Vectors... Display Reports... Verbose
7. Click 3. Turn ON
Window
File
Cancel
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6. Click
an
4. Turn ON
JTAG Assertions Methodology ATPG Conicts Ports Constraints Scan Path Coverage Dont Fault Faults Fault Options: Untested
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2. Click
Cancel
C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help
C Command Window
design_analyzer>
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For illustration purposes, assume that the core RTL model has the ports input I; output O1; output [3:0] O2; Suggested names for chip Verilog le and module are designchip.v and designchip, respectively. In both the chip module and the core component instantiation, include all the ports in the core Verilog model, and also add the following two ports :
input test_si, test_se;
TUTORIAL STEP
module testchip (test_si, test_se, RST, CLK, ACI, ACO); input test_si, test_se; input RST, CLK; input [2:0] ACI; output [2:0] ACO; test c_core (.test_si(test_si), .test_se(test_se), .RST(RST), .CLK(CLK), .ACI(ACI), .ACO(ACO)); endmodule;
For pads with output enables, - Declare a variable to control the output enable:
reg pads_oe;
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For illustration purposes, assume that the core RTL model has the ports I: in std_logic; O1: out std_logic; O2: out std_logic_vector(3 downto 0); Suggested names for chip VHDL le and entity are designchip.vhd and designchip, respectively. In both the chip entity and the core component declaration, include all the ports in the core RTL model, and also add the following two ports :
test_si: in std_logic; test_se: in std_logic;
TUTORIAL STEP
entity testchip is port ( test_si, test_se: in std_logic; RST, CLK: in std_logic; ACI: in std_logic_vector (2 downto 0); ACO: out std_logic_vector (2 downto 0)); end testchip; architecture behav of testchip is
For pads with output enables, - Declare a signal to control the output enable:
signal pads_oe : std_logic;
component test port ( test_si, test_se: in std_logic; RST, CLK: in std_logic; ACI: in std_logic_vector (2 downto 0); ACO: out std_logic_vector (2 downto 0)); end component; begin c_core: test port map (test_si=>test_si, test_se=>test_se, RST=>RST, CLK=>CLK, ACI=>ACI, ACO=>ACO); end behav;
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Step 4.3 (Analyze the chip hdl_le)1 Step 4.4 (Elaborate the chip entity or module)2 Step 4.5 - Step 4.7 (Constrain the chip design)3
1hdl_le
test_chip.v (test_chip.vhd)
For the Analyze command hdl_le(s), select/specify the chip HDL le you created in Step 4.17/Step 4.18. Do not specify the core design HDL le. All other information is the same as for the previous (core design) Analyze command execution.
2entity/module
test_chip For the Elaborate command entity or module, select the select/specify the entity or module name of thechip HDL model created in Step 4.17/Step 4.18. Do not specify the core deisgn entity or module. If you use a different architecture name for the chip design, remember to specify it, otherwise all the other information is the same as that when you executed athe Elaborate command for the core design.
3For
command-line execution, when you run the set_test_methodology command, remember to run it wih the option -exisiting_scan to tell Design/Test Compiler that the design already contains scan circuitry. For example, to set test methodolody to full scan, run the command as follows: set_test_methodology full_scan -existing_scan
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives CLK I1 I2 O1 O2 Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...
C Command Window
set_dont_touch instance_name
2. Select
T
design_analyzer>
1. Click
3. Turn ON
5. Click
c_core instance_name The name of the instance of the core design in the chip. Note that this is not the design (entity or module) name of the core, but rather the name of the instance or component when it is instantiated in the chip design.
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives
T
C Command Window Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...
set_port_is_pad *
design_analyzer>
Design Name: Ungroup Boundary Optimization Sequential Elements: Port is Pad: Test Scan Style:
Flip Flop...
Flatten Logic Flatten Effort: Flatten Minimize: Flatten Phase: Low Medium High Single Output Multiple Output None Dont Apply Apply Strategy 2. Click
Structured Logic Apply Timing Driven Structuring Apply Boolean Optimization Apply Cancel
3. Click
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Delete Insert Pads... Select... Unselect All Group... Ungroup... Uniquify Reset... Help
C Command Window
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...
C Command Window
1. Click
O1 O2
Port Name:
selected_port
Maximum Fanout: Maximum Transition: Port is Pad: Connected to: Set Equal... Test Hold: Signal Type: Apply Port Pad Attributes... Logic 0 Logic 1
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3. Select Test Scan Enable 5. Select Pin test_si 6. Select Test Scan In
4. Click
C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives CLK I1 I2 test_se test_si Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...
C Command Window
design_analyzer>
O1 O2
Apply 4. Click
Cancel
O scan_out The design output pin that is also used (multiplexed) as a scan output pin. This pin was reported in Step 4.15 when you run the report_test command.
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Maximum Transition: Port is Pad: Unonnected 3. Click Signal Type: Scan Out Port Pad Attributes...
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Perform this step twice: rst for the HDL format (e.g. verilog), and then for the export format (e.g. edif)
C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help 1. Type le_name or 1. Select le_name C Command Window
File Name: Directory: /home/... ../(Move up one directory) le1 le2 le3 le4 File Format: DB
2. Select le_format
test_g.v le_name The name of the le that the design has to be saved as. When saving the HDL gate-level le, make sure that you specify a different le name from the one containing behavioral design. verilog le_format The format in which you want the design to be saved. Valid formats are: db Synopsys internal database format vhdl IEEE Standard VHDL verilog Cadence Verilog HDL edif Electronic Design Interchange Format xnf Xilinx Netlist Format mif Mentor Interchange Format (MIF) equation Synopsys equation format st Synopsys State Table format tegas Tegas design Language netlist Fornat lsi LSI Logic Corporation Netlist Format pla Berkeley (Espresso) PLA format
3. Turn ON
4. Click
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help
C Command Window
test_default_period = default_period test_default_delay = default_delay test_default_strobe = default_strobe create_test_clock clock_pin -period period -waveform {rise_edge fall_edge}
design_analyzer>
CLK clock_pin Pin to be used as clock during test. 100 period Value of the period of the test clock in ns.
45 55 rise_edge fall_edge Rise and fall edge times of the test clock over one period (typically, the rst edges after time zero).
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T
C Command Window
Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... 2. Click Test Manager... Format Vectors... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel Test Pattern Generation Options: Use Initial Pattern File: Display Reports... Cancel Verbose
5. Click
Compact Patterns Efoort: Low (Backward) Contention Check Float Check Additional Options...
3. Click
Background Cancel
OK
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design.vdb
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window
Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... 2. Click Test Manager... Format Vectors... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel Mask Faults Methodology Ports Scan Path Timing (TestSim) Display Reports... Cancel Verbose
3. Turn ON
Coverage Faults Fault Options: Untested Report Scope: All (Cumulative) Send Output To: File: Last (Incremental) Window File
4. Type untested
5. Click 6. Click
Apply
Cancel
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T
C Command Window
Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager... Format Vectors... Display Reports... Cancel Input Pattern File: Output File: Format: design.vdb design Parallel 3. Optionally1 Turn ON/OFF 1. Click
5. Click
synopsys
wgl vector_format One of the following supported vector formats: vhdl, verilog, wgl (TSSI WGL), tds (TSSI TDS ASCII), synopsys (Synopsys generic), mif (Mentor Interchange Format (MIF)), pla (Berkeley (Espresso) PLA format).
1-parallel
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4. Click
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OK
Cancel
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Only Format Current Test Program Format Entire Test Program Sequence
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help
C Command Window
design_analyzer>
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hcells link_library A technology library specied in the link_library variable. If there are more than one library specied, run the write_testsim_lib command on each library, one at a time.
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hcells.sdb symbol_library The le of the symbol library that have the same root name with one of the link libraries. Run the free command on all such symbol libraries before running the next command.
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T
C Command Window
Full Scan
Partial Scan
Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... 2. Click Insert Boundary (JTAG) Scan Circuitry... Test Manager... Verbose
Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel 9. Click 3. Type design_chip.vdb
10.Click Pre Fault Simulation Check: Verify Timing Parameters Fault Simulation Context: Input Vectore File: Input Format: Output Test Program: Save TestSim Model File: Use TestSim Model File: Signal Defn. (SDF) File: On Off Stuck-at Faults: Mode: Evaluate Probables Normal On Off IDDQ Defects: IDDQ Defect Model: Node Toggle Transistor Shorts Maximum Measurements: Incremental Coverage %: OK 8. Click vdb
5. Turn ON
6. Type parallel
7. Type design_chip_testsim.db
Cancel
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Format Vectors...
C Command Window
report_test -coverage -faults -class untested restore_test design_chip.vdb report_test -coverage -faults -class untested
design_analyzer>
Full Scan
Partial Scan
Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... 2. Click Insert Boundary (JTAG) Scan Circuitry... Test Manager... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel 7. Click 3. Turn ON Restore Test Program Name: delete Current Test Program Apply Cancel 8. Click Format Vectors... Display Reports... Cancel Verbose
4. Type design_chip.vdb
5. Click 6. Click
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C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T
C Command Window
Full Scan
Partial Scan
Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... 2. Click Insert Boundary (JTAG) Scan Circuitry... Test Manager... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel 9. Click 3. Type design_chip_0.WGL Format Vectors... Display Reports... Verbose
10.Click Pre Fault Simulation Check: Verify Timing Parameters Fault Simulation Context: Input Vectore File: Input Format: Output Test Program: Save TestSim Model File: Use TestSim Model File: Signal Defn. (SDF) File: On Off Stuck-at Faults: Mode: Evaluate Probables Normal On Off IDDQ Defects: IDDQ Defect Model: Node Toggle Transistor Shorts Maximum Measurements: Incremental Coverage %: OK 8. Click wgl
4. Select wgl
5. Turn ON
6. Type serial
7. Type design_chip_testsim.db
Cancel
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test design The root name of your design. CLK clock_pin Pin to be used as the test clock.
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5
Simulate the Gate-Level HDL Netlist
Verify the Functionality and Timing of the Synthesized Circuit
a b clk d q c clk b o
After synthesizing the circuit, it is important that you run the simulation on the resulting circuit in order to verify that the design still meets the intended functionality and timing. The simulation is run similarly to the way it was done for behavioral simulation (Section 4/5), except that now you make use of the timing models of the gates in the target library.
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TUTORIAL STEP
dene library_name dir=sim_model_dir uselib library_name timescale unit_time/resolution_time where, library_name The name you choose to give the library. Again, this doesnt have to be the same name as the actual name of the library - it is simply a symbolic name. Example MYLIB, KCELLS, etc. sim_model_dir The full path of the directory containing the simulation models of the target library gates. For example, for the cmosis technology, the path is are /CMC/kits/ cmosis5/synopsys/cmosis5.1.1/verilog/nwb and /CMC/kits/cmosis5/synopsys/cmosis5.1.1/verilog/ udp. unit_time The unit of time to be used in the simulation e.g 1ns. resolution_time The simulation resolution, to the unit time. For example, if the unit_time is 1ns, and a resolution of 0.01ns is required, specify resolution_time as 10ps.
dene HCELLS dir=/CMC/kits/cmosis5/synopsys/cmosis5.1.1/verilog/nwb dene HCELLUDP dir=/CMC/kits/cmosis5/synopsys/cmosis5.1.1/verilog/udp uselib HCELLS HCELLUDP timescale 1ns/10ps
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Step 3.2/5.X (Run the Simulation)1 Step 3.3 - Step 3.4/5.X (View the Waveforms)2
Errors, Warnings, & Reports Warning: Too few module port connections... - Manually add the scan test ports (test_se, test_si, and test_so) in the port mapping of the instance of your design in the test bench as suggested above. Warning: Implicit wire has no fanin ... - If this warning is on the three scan test ports mentioned above, simply add the two statements (reg test_se, test_si; and wire test_so;) in the test bench. Otherwise, the warning means that some of the module ports are not connected to anything.
1When
running the simulation, your design le (design.v or design.vhd) must now be the gate-level netlist le created in Step 4.26 (design_g.v or design_g.vhd).
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6
Import the Design to Cadence
Import the HDL or EDIF Netlist to Cadence DFII
wire n1; hnd2 u1 (.op(n1), .p1(a), hdrpq u2 (.q(O), .d0(n1), endmodule a b clk d q c
Now that both the functionality and gate-level timing of the design has been veried, the design is imported to Cadence for cell placement and routing. The design can be imported using the gate-level HDL or EDIF netlist. In this manual, the design is imported using Verilog netlist.
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To start the Cadence, at the Unix prompt, type: startCds -t technology where, cmosis5 technology The name of the target technology. This must be the same technology that was used to synthesize the design in Synopsys (Step 2.1). Valid technology names (supported by CMC) are: cmosis5 - 0.5 m CMOS. cmosp35 - 0.35 m CMOS. bicmos - Nortel 0.8 m BiCMOS. mitel15 - Mitel 1.5 m CMOS.
TUTORIAL STEP
startCds -t cmosis5
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C icfb - Log:... (CIW) File Tools Options Technology File CMC Gateway CMOSIS5 Help Conversion Tool Box... Library Manager... C Library Manager: Library Path Editor... File Edit View Design Manager Help CheckPlus... New Categories Library... Show Verilog-XL Integration... Open... Cell View... VHDL Tool Box... View Cell Library Open (Read Only) Category... Synergy Tool Box... abstract padvddrcc Open Shell Window basic Synopsys Integration... extracted cdsDefTech padvddring Exit Tantools... layout padvsscore cmcpads Display Resources schematic padvssrcc cmosis5 Mixed signal EnvironLibrary verilog padvssring designFlow Switched Capacitor Name: Automatic Cell CharaMessages DANTES Directory P&I Library Tools .. CDF 1. Type dir1 design_lib Design Flows dir2 Camera dir3 SKILL Development... Design Manager 2. Click Use OK 3. Turn ON OK 4. Click Cancel Help No DM Apply Cancel Help
Technology File for library design_lib If you will be creating mask layout or other physical data in this library, you will need a technology le. If you plan to use only schematic or HDL data, a technology le is not required. You can: 6. Click Compile a new techle Attach to an existing techle Dont need a techle
5. Select tech_lib
DESIGNS design_lib Name of your design library. cmosis5 tech_lib The technology library, e.g. cmosis5, cmosp35, bicmos, mitel15.
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C icfb - Log:... (CIW) File Tools Options New Open... Import Export Refresh... Make Read Only... Whats New... Exit... Technology File CMC Gateway CMOSIS5 Help
1. Type design_lib
2. Type shadow_libs
EDIF... Verilog... VHDL... CALMP... Help SDL... OK Cancel Defaults Apply Load Save CDL... File Filter Name DEF... LEF... ../ dir1 TEGAS... dir2 SILOS... dir3 Stream... Browse CIF... Target Library Name Applicon... Reference Libraries Verilog Files To Import -f Options Add Add Add Add
10.Click
!
OK
9. Click
OK Cancel Defaults Apply Sheet Symbol Maximum Number Of Rows none 1024
Help
8. Click
Maximum Number Of Columns 1024 Font Hieght Line To Line Spacing Line To Component Spacing Component Density 0.0625 0.2 0.5
Lowest Highest
3. Type design_le
4. Type nwb_dir
Ignore Modules File Import Structural Modules As Structural Vie Names Schematic schematic Netlist Symbol netlist symbol schematic
Add Pin Placement Left and Right Sides Import As Functional Pin Placement FileName 7. Type VSS! Full Place and Route Generate Square Schematics Minimize Crossovers Optimize Wire Label Locations Extract Schematics Global Nets Power Net Name Global Signals
All Sides
5. Click
Import
6. Type VDD!
DESIGNS design_lib Name of the design library to import the design into (or the one you created in Step 6.2). _hcells _cmcpads shadow_libs Shadow libraries (described at the beginning of this step). test_g.v design_le The Verilog le to import. This is the gate-level netlist le you saved in Synopsys in Step 4.26. /CMC/tools/cadence/tools/dfII/local/lib/cmosis5/models/verilog/nwb nwb_dir The Cadence directory that contains the Verilog models of the cells in the technology libraries.
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File Tools Options Technology File CMC Gateway CMOSIS5 Help New Open... Import Export Refresh... Help OK Cancel Defaults Make Read Only... Whats New... Cell Names Library Name design_lib 1. Select Exit... design_lib cell1 Cell Name cell_name cell2 cell3 schematic View Name cell4 2. Select Browse cell_name read edit Mode Library Path File your_design_directory/cds.lib 3. Select schematic
4. Click
DESIGNS design_lib Name of your design library. test_chip cell_name The name of your design. This is the name you gave to the top-level module (Verilog) or entity (VHDL). Note that this is NOT the name of the imported Verilog le (even though these two might sometimes be the same).
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C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Current Cellview Hierarchy... Options... Rules Setup... Label Attachment... Find Marker... 1. Turn ON Delete Marker Delete All Markers... Schematic Monitors 2. Click OK Cancel Defaults Apply Packaged Checks Logical Checks None Name Checks ignored ignored ignored ignored ignored ignored ignored warning warning warning warning warning warning warning error error error error error error error
Help
Floating Nets Floating Input Pins Floating Output Pins Floating I/O Pins Floating Switch Pins Shorted Output Pins Offsheet Connector Check Physical Checks Unconnected Wires Solder On CrossOver Overlapping Instances Percent Overlap Allowed Maximum Label Offset Max Distance from Wire
Instance/Net Name CollisPin/Net Name Collision Verilog HDL Syntax VHDL Syntax AHDL Syntax Instance Name Syntax Instance Name Expression Pin Name Syntax Pin Name Expression Net Name Syntax Net Name Expression
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C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Schematic Layout/Extract Check Supply IO Check and Save Design Hierarchy P&R RET
Errors, Warnings, & Reports Warning: Unable to enter/create cellview... - Ignore these warnings
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C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Component... Wire (narrow) Wire (wide) Wire Name... Pin... 1. Click Help Hide Cancel Defaults Block... Solder Dot Library Name Browse Cell Names Note View Name Instance Names Array Rotate Columns Upsidedown Rows Sideways 2. Select cmcpads C Library Manager: File Edit View Design Manager Show Categories Library basic cdsDefTech cmcpads cmosis5 designFlow Messages 5. Click1 Cell padvddrcc padvddring padvsscore padvssrcc padvssring View abstract extracted layout schematic symbol 4. Select symbol Help 3. Select padvddrcc
1To
place the selected component in the schematic, simply left-click anywhere in the schematic editor window. But make sure that the component does not touch other parts of the circuit.
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C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Schematic Layout/Extract Check Supply IO Check and Save Design Hierarchy P&R RET
Errors, Warnings, & Reports Warning: Failed to open cellview... - Ignore these warnings Report: IO check OK. - If you dont get this report in the CIW, then there is something you have done wrongly. You should correct the mistake you made, or simply redo all the steps from Step 6.3.
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C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Current Cellview Hierarchy... Options... Rules Setup... Label Attachment... Find Marker... Delete Marker Delete All Markers... 1. Click Schematic Monitors
Errors, Warnings, & Reports Warning: Pin WORLD on ... oating ... - Ignore these warnings
OK
Cancel
Defaults
Apply
Help
only those that need it every schematic check do not check yes SpectreS no those with errors Ask Me extracted schematic symbol
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7
Place and Route the Design
Place and Rout the Design Using Cell Ensemble
a b clk d q c
In this step, you will layout the chip. First, the pads and gates are placed, and then the design is routed.
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C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Analog Artist Datapath/Schematic Design Synthesis Diva Floorplan/Schematics Mixed Signal Opts. Module Maker Schematics Simulation
C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Floorplan CMC Skill He Hierarchy Browser... Cross Select Cross Highlight 1. Click
OK
Cancel
Defaults
Apply
Help
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C Hierarchy Browser: ... Window Utilities Hierarchy Help Deselect All Cross Select Cross Highlight Environment...
OK
Cancel
Defaults
Apply
Help
======Display Options====== Instance Node Label Instance Filter Instance Count On Node Tree Expansion Direction Tree Routes Fit Tree Graphics in Window ======Expand Options====== Levels
instance name master name IO block core cell vertical levered horizontal fan
1 all
======Generate AutoLayout/AutoAbstract Options====== Default Area Estimation Function Default Area Utilization (%) Default Area Per Gate simple 80 10 1. Click
Change Default Global Signal Names Obstruction On Block Hierarchy Delimiter Character
OK
Cancel
Defaults
Apply
Library To Store New Global Names Global Power Signal Name Global Ground Signal Name Use Existing Global Names vdd! gnd! in Library
3. Click
cmosis5 tech_lib The technology library, e.g. cmosis5, cmosp35, bicmos, mitel15.
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C Hierarchy Browser: ... Window Utilities Hierarchy Expand Selected Unexpand Selected Generate Physical Hierarchy Generate Abstract From Symbol Properties Help
Errors, Warnings, & Reports Report: The layout hierarchy has been created successfully. - If you dont get this report in the CIW, then there is something you have done wrongly. You should correct the mistake you made, or simply redo all the steps.
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File Tools Options Technology File CMC Gateway CMOSIS5 Help New Open... Import Export Refresh... Help OK Cancel Defaults Make Read Only... Whats New... Cell Names Library Name design_lib 1. Select Exit... design_lib cell1 Cell Name cell_name cell2 cell3 schematic View Name cell4 2. Select Browse cell_name read edit Mode Library Path File your_design_directory/cds.lib 3. Select autoLayout
4. Click
DESIGNS design_lib Name of your design library. test_chip cell_name The name of your design.
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C Virtuoso Editing: ... Tools Design Window Create Edit Verify Misc CMC Skill Abstract Analog Artist Compactor Device-Level Editor Device-Level Router Floorplan/P&R Base Array Editor InQuery Block Ensemble Layout Cell Ensemble Layout Synthesis Cell3 Ensemble Microwave Datapath/Cell Ensemble Module Maker Datapath/Cell3 Ensemble Pcell Gate Ensemble Simulation Structure-Compiler Verilog-XL Help
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Reinitialize... I/O Place... Partition Block Place... Soft Pins Update AutoLayouts... Floorplan File Synthesis Link Replace View... Help
OK
Cancel
Defaults
Apply all regions chip size special routing IOs macros lower left
Initialize
Preserve pre-placed Chip Origin Estimate Design Size Chip Aspect Ratio (Width/Height) Load a Floorplan File Load a SDF File
1. Type 0.8
2. Click
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC IO Commands Automatic... Qplace... CTS Place... Spare Cell... Power Cell Glue Cell Snap To Grid... Sequencer... 1. Click Check... Help
OK Cancel Defaults Apply Method Insert Feedthru Feedthru Library Name hcells Feedthru Master Name hft Feedthru Master View Placement Snap Grid Mirror Cells Browse Options Initial Improve abstract 0.1 initial improve
Help both
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Read Initial File... Justify... Add Corners... Place Route CMC IO Commands Automatic... Qplace... CTS Place... Spare Cell... Power Cell Glue Cell Snap To Grid... Sequencer... Check... Help
OK Cancel Defaults Apply Glue Cell Library Name cmcpads Glue Cell Master Name Glue Cell Master View abstract Browse Net Association match TermName none
Help
1. Type CORNERc
2. Type ./glue.map le
3. Click
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Display Cutlines... Channels Remove Cutlines... Modify Net Create... Special Net Route Delete Global Route Detail Route Sequencer... 1. Click Check... Help
OK Cancel Defaults Apply Initial Cut Channel Name Cut With Barriers vertical Channels horizontal
Help automatic
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Channels Modify Net Properties... Modify Net Special Net Route Net Properties File... Global Route Split Net Detail Route Unsplit Net Sequencer... Check... Help
1. Turn ON OK Cancel Defaults Apply Net Properties File Nets Properties File Name Properties To Save write all P&R Help read selected 2. Turn ON all 3. Type ./net.props
4. Click
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Channels Modify Net Special Net Route Global Route Automatic... Detail Route Delete... Single Net Global Route... Sequencer... Interactive Global Route... Check... Display Channel Density... Remove Channel Density... Adjust Channel Density... Topology Display... Global Routing File... 1. Click Help
Errors, Warnings, & Reports Error: ..auiGetBoolFieldValue error.. - Ignore this error.
Help optimize
Optimizer
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Channels Modify Net Special Net Route Global Route Detail Route Switch Layer... Sequencer... Reserve Tracks... Check... Automatic... Delete... Explode Channels 1. Click Strip Outer Channels... Help
Errors, Warnings, & Reports Error: ..auiGetBoolFieldValue error.. - Ignore this error.
OK Cancel Defaults Apply Compaction Mode Contact Style Add Conditional Via Tie Pin To Cell Instance Routing Layers automatic centered rigid offcentered
2 or 2 1/2 Layers
3 Layers
Max Vert Jog Length for half-layer Max Horiz Jog Length for half-layer Options Compact
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Help Schematic Layout/Extract Slot wide metal3 busses P&R RET Flatten SymbolicVias
C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Help Schematic Layout/Extract Slot wide metal3 busses P&R RET Flatten SymbolicVias
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Reinitialize... I/O Place... Partition Block Place... Soft Pins Update AutoLayouts... Floorplan File Synthesis Link Replace View... Help
OK
Cancel
Defaults
Help all
3. Click
2. Select layout
1. Turn ON
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C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Save Save As... Discard Edits Load... Make Read Only Show Selected... Hierarchy Plot Options Environment Help
C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Help Save Save As... Discard Edits Load... 1. Type Make Read Only 2. Click layout Show Selected... Hierarchy Plot Help Apply OK Cancel Defaults Options Environment Library Name DESIGN Cell Name View Name test layout
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C icfb - Log:... (CIW) File Tools Options Technology File CMC Gateway CMOSIS5 Help CMC-Added Documentation On Connecting to CMC On Getting Help with Cadence Tools Bug Submission Form Start Cadence Documentation Place Logo
1When
opening the layout view, make sure you select layout on the View Name.
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