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Introduction
Introduction, Design Example and Manual Conventions
Verilog or VHDL Constraints Simulation Synthesis Libraries

This sections describes what the manual is about. It outlines the design methodology used, and gives a description of the design example used in the tutorial. The convetions used in the manual are also described.

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1.1 About This Manual


This manual describes the basic digital IC design ow using Synopsys 3.4b and cadence 9504 tools. The manual can either be used as a general guide for designing with different technologies supported for synthesis by CMC, or it can be used as a CMOSIS5 (Hewlett Packard 0.5 m CMOS technology) tutorial using the design exeample described Step 1.2. This manual is not intended to be a replacement of the reference manuals for the respective tools, but rather as a quick guide for a simple design process to take a design from HDL to the nal layout. Figure 1.1 shows the design methodology.

Specications VHDL or Verilog Behavioral Simulation Synthesis & Test Gate-Level Simulation
SYNOPSYS CADENCE

Libraries & Constraints

Place & Route Design Verication Stream File


Figure 1.1 Design Methodology

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1.2 Tutorial Design Example


A very simple example is given here for use in the tutorial. It is basically a 3-bit accumulator (i.e. its output is incremented by its input on each positive clock edge; the output is reset to zero when RST is high). The design name is called test. Shown below are the block diagram and the corresponding Verilog and VHDL code of the design.

+
ACI 3 CLK RST

ACO 3

VHDL (test.vhd)
entity test is port ( RST, CLK: in std_logic; ACI: in std_logic_vector(2 downto 0); ACO: out std_logic_vector(2 downto 0); end alu; architecture behav of test is signal ACC: std_logic_vector(2 downto 0); ACC_PROC: process (RST, CLK, ACI, ACC) begin if (RST = 1) then ACC <= (others => 0); elsif (CLKevent and CLK = 1) then ACC <= ACC + ACI; end if; end process ACC_PROC; ACO <= ACC; end A;

Verilog (test.v)
module test (RST, CLK, ACI, ACO); input RST, CLK; input [2:0] ACI; output [2:0] ACO; reg [2:0] ACO; always @(posedge CLK or posedge RST) begin if (RST) ACO = 0; else ACO = ACO + ACI; end endmodule

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1.3 Manual Conventions


The following conventions are used in the manual.

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2
Setup the Design Environment
Synthesis and Simulation Setup Files
target_library = {kcells.db pads.db} link_library = {. kcells.db pads.db} symbol_library = {kcells.sdb} edifout_netlist_only = true

In this step you setup the synthesis and simulation design environment by using the Synopsys setup les. Some of the variables that need to be specied before you can run synthesis and gate-level simulation include the technology and symbol libraries of the target technology, gate-level simulation libraries, as well as the search path to these and other libraries and design references.

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2.1 Copy A Sample Synthesis Setup File


There are a number of variables that need to be set before you can run the Synopsys synthsis tools. These variables are set in the .synopsys_dc.setup le. Fortunately, almost all technologies that support Synopsys synthesis comes with a sample synthesis setup le. You must copy this le into your design directory and name it .synopsys_dc.setup.

Go to your design directory cd design_dir Copy the sample synthesis le from the directory containing the technology design kit for Synopsys. cp /CMC/kits/technology/synopsys/technology.version/dotles/dc_dot_le .synopsys_dc.setup

TUTORIAL STEP

At the Unix prompt, type:

cd design_dir cp /CMC/kits/cmosis5/synopsys/cmosis5.1.1/dotles/.synopsys_dc.setup .synopsys_dc.setup

design_dir Your design directory technology The name of the technology you are targeting. Examples are bicmos, mitel15, and cmosis5. version The version of the technology CMC design kit for Synopsys. Examples are 1.1 and 2.1 dc_dot_le The name of the sample synthesis setup le. In some technologies this sample le is given the name .synopsys_dc.setup (i.e. it is a hidden le and hence you have to list all dot les in order to check if it exist - use the Unix command ls .synopsys_*), while in others, the name is usually target_lib.synopsys_dc.setup, where target_lib is the name of the target library in the technology, e.g. kcells in the bicmos technology.

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2.2 Verify/Edit the Synthesis System Variables


Open the .synopsys_dc.setup le in an editor to verify/edit it to make sure that the synthesis system variables described below are set correctly. Note that apart from these variables, the setup le might contain other variables such as bus naming and EDIF options. Variables not described below should be left unchanged.

search_path This species the directories to be searched by the synthesis tools for les. It should include at least the following:
search_path = {. design_kit_dir//syn synopsys_dir/libraries/syn}

TUTORIAL STEP

where . indicates the directory you started the synthesis tools from (your design directory) target_library Species a list of technology libraries of components used when compiling a design.
example: target_library = {hcells.db}

company = put_your_company_name_here designer = put_your_name_here search_path = {. /CMC/kits/cmosis5/synopsys/ cmosis5.1.1/3.4b/syn /CMC/tools/synopsys.3.4b/ libraries/syn} target_library = {hcells.db} link_library = {* hcells.db} symbol_library = {hcells.sdb}

link_library Species a list of design les and libraries used during linking. Linking resolves design references by connecting the design to all library components and designs it references. For this reason include an asterisk (*) in the list to include all the designs in your design library.
example: link_library = {* hcells.db}

symbol_library Species the libraries that contain the graphical information of symbols of components used when displaying the schematic of a compiled design. Files for symbol libraries usually end in .sdb extension.
example: target_library = {hcells.sdb}

designer Your name (the designer). This is displayed on the design schematics.
example: designer = Peter Nyasulu

company The companys name where the Synopsys tools are installed. It is also displayed on design schematics.
example: company = Carleton University

design_kit_dir The directory containing the technology design kit for Synopsys. Normally it should be /CMC/kits/technology/synopsys/technology.version, where technology is the name of the technology (e.g mitel15, bicmos, cmosis5) and version is the kit version (e.g. 1.1) synopsys_dir The Synopsys tools root directory. Normally it should be /CMC/tools/synopsys.3.4b.

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2.3 Setup the Synopsys VSS Simulation (VHDL Only)


Most of the variables required to simulate a design using the Synopsys VHDL System Simulator (VSS) are already setup correctly in the Synopsys generic VSS setup le (.synopsys_vss.setup). However, there are still a few variables that need to be customized for your design simulation. Firstly, for gate-level simulation, you need to specify the path to the Full Time Gate-level Simulation (FTGS) libraries of your target technology. FTGS libraries contain both the gate functionality as well as gate delays. You may also optionally specify the time step of the simulation.

Go to your design directory cd design_dir Using your favorite editor, open/create the le .synopsys_vss.setup. For example, if you are using emacs editor, type the following at the Unix prompt: emacs .synopsys_vss.setup & In the le, specify the following variables: FTGS Library This denes the names of the libraries to be used in the RTL le for gate-level simulation, as well as the path to the actual FTGS libraries (the dened library name doesnt have to be the same as the actual name of the library). You must dene this for each of the target library used in your design (libraries specied in the target_library variable in .synopsys_dc.setup le). Syntax: gate_library: /CMC/kits/technology/synopsys/ technology.version/sim/target_library_name Example (when using the cmosis5 technology): hcells: /CMC/kits/cmosis5/synopsys/cmosis5.1.1// 3.4b/sim/hcells Simulation Time Base/Resolution The units and resolution of the simulation times. For example, to set simulation units to nanoseconds, and the resolution to 100 picoseconds, add the following lines in the setup le: TIME BASE = NS TIME_RES_FACTOR = 0.1 Editor Editor that synopsys invokes when you execute any of the Synopsys environment edit le commands. The default editor is set to vi. For example, to set the editor to Emacs, include the following line in the setup le (assuming emacs is the command that is used to invoke the Emacs editor): EDITCMD = emacs

TUTORIAL STEP

hcells: /CMC/kits/cmosis5/synopsys/cmosis5.1.1// 3.4b/sim/hcells TIME_BASE = NS TIME_RES_FACTOR = 0.1 EDITCMD = emacs

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3
Simulate the Verilog RTL Model
Verify the Functionality of the RTL Model
always @(posedge clk) begin c = a & b; end clk b o

In this step you verify the functionality of the Verilog behavioral model by simulating it using Cadence Verilog-XL Simulator. You can print the results of the simulation (in text format) using the in-built Verilog system tasks, or you can view the signals waveforms using Cadence Cwaves waveform viewer.

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3.1 Setup the Design Test Bench for Cadence Cwaves


While it is possible to simulate a design as a stand-alone, it is advisable to simulate using a test bench. Simulating a design using a test bench simplies the task of specifying the simulation stimuli (since these are described in the same style and language as the design itself), and, more important, you can then use the very same test bench to simulate the gate-level model (Section 6). For more information on how to write a test bench, see the example in the manual Introduction to Verilog. To use the Cadence Cwaves waveform viewer, you must include the following Cadence-specic Simulation History Manager (SHM) tasks in the test bench (This is again illustrated in the test bench example in the Introduction to Verilog manual):

initial begin $shm_open (database_directory) $shm_probe (var1, var2, ..., varn) end where, database_directory The name of the directory where the waveforms data should be stored. Enclose the name in double quotation marks. var1, var2, ..., varn The list of Verilog variables whose waveforms should be evaluated and stored. You can then later choose which of these waveforms you display in the waveform viewer. Note that any variable that is omitted from the probe list cannot be viewed in cwaves without having to re-run the whole simulation.

TUTORIAL STEP

In the test bench, include the following lines:

initial begin $shm_open (shm_waves) $shm_probe (RST, CLK, ACI, ACO) end

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3.2 Run the Simulator and Open the Waveform Viewer


Run the Verilog-XL simulator by specifying both the test bench and the design verilog les. This will compile the Verilog source les, and if there are no errors, view the waveforms by running cwaves. While it is possible to simulate a design as a stand-alone, it is advisable to simulate using a test bench. Simulating a design using a test bench simplies the task of specifying the simulation stimuli (since these are described in the same style and language as the design itself), and, more important, you can then use the very same test bench to simulate the gate-level model (Section 6).

To start the Cadence-XL simulator, at the Unix prompt, type: verilog design_tb.v design.v where, design_tb.v The name of the test bench Verilog source le. design.v The name of the design Verilog source le.

TUTORIAL STEP

At the Unix prompt, type:

verilog test_tb.v test.v cwaves &

To start the Cadence Cwaves waveform viewer, at the Unix prompt, type: cwaves &

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3.3 Load Data for the Waveforms


Load the data for the waveforms into the Cadence Cwaves waveform viewer. This is done by specifying the directory you used in the $shm_open task in your test bench as the le name.

C Cadence Cwaves File Edit View Options Load Data... Plot... Save Setup... Restore Setup... Close Data Quit Help

Errors, Warnings, & Reports

1. Type in shm_dir

File Path: File Name: Server Host Name: OK Cancel Apply Help

2. Click

shm_waves shm_dir The name of the directory that was specied in the $shm_open task in the test bench. Note that this directory name is typed in the File Name eld, and not in the File Path eld. The default in the File Path eld is a dot (.), which means the directory where you started cwaves from. If this is not the directory where the shm_dir is, you must specify the full path of the directory in this eld. The default for the Server Host Name, which is usually localhost, should sufce.

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3.4 Select and Display Signals


Select the signals you want to display and display them in the waveform viewer. Normally, the shm_dir contains the waveforms of so many signals, but you might only want to display a few of these at a time. In this step, you can add, delete, or group waveforms into the waveform viewer.

C Cadence Cwaves File Edit View Options Browser/Display Tool... Add Signal By Name... Cut Copy Paste Delete Strips Signals Markers Viewports Comments Logic Overlay Display Values... 1. Select design_tb Help

Errors, Warnings, & Reports

Mode:

Display

Cancel Grouped Waveforms Group: Display group0 New...

Help

Hierarchical Signal Browser Simulation Data Current Scope Display

Delete Group

design_tb

2. Click var1 var2 varn

3. Select varn

4. Click

test_tb design_tb The module name of the test bench. Select it by leftclicking once on it. Once the test bench module name is selected, the subscope up/down buttons, which you are supposed to click in step 2, will be activated. RST, CLK, ACI, ACO var1, var2, ... The variables whose waveforms are to be displayed. Repeat steps 3 and 4 for each of the variable you want to display. Alternatively, you may select all the signals at once in step 3 by clicking on the rst variable, then hold down the shift button, and click on the last.

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Subscopes Add Selections Strips

Signals

Delete Signals

5. Click

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4
Synthesize the RTL Model
From RTL to Schematic/Netlist
always @(posedge clk) begin c = a & b; end a b clk d q c

This step will convert the RTL model of your design into a netlist (and schematic) using the cells in the target technology library. The design is also optimized for timing and area. Synopsys power optimizations are only possible with ECL designs and hence are not covered in this manual.

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4.1 Start the Synopsys Design Analyzer


Synopsys Design Analyzer provides a graphical (menu-driven and command-line) interface to the Synopsys tools you will be using during synthesis (VHDL Compiler, HDL Compiler, Design Compiler, Test Compiler, Design Time).

To start the Design Analyzer, type the following at the Unix prompt (The & starts the Design Analyzer in background so that you can use the Unix window for other commands): design_analyzer & Optionally, you can use the Design Compiler (dc) shell and run the synthesis using dc shell commands only. Since the dc shell is a text-based window, you will not be able to see the schematic. It is therefore not advisable to use the dc shell unless you are very experienced with it. To start the dc shell, type the following at the Unix prompt: dc_shell

Errors, Warnings, & Reports

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4.2 Open the Design Analyzer Command Window


Design Compiler (dc) shell commands can be executed using the Design Analyzer command window. Design Compiler commands are usually easier to execute than their Design Analyzer menu equivalents. They can also be collected up in a le to be executed as a script in either the dc shell or the Design Analyzer command window. The command window is also used as a report window for all commands executed in the Design Analyzer. Therefore, after executing a command (using either the command window or the Design Analayzer menus),you must always check the results the report generated in the command window. It is easier to debug and correct errors at an earlier stage of synthesis.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Defaults... Variables... License Execute Script... Scripts T Command Window...

C Command Window Help

design_analyzer>

Errors, Warnings, & Reports

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4.3 Analyze the RTL Model


Analyzing the RTL model checks the syntax of the VHDL/Verilog model, checks if VHDL/Verilog constructs not supported for synthesis are used in the model, and converts the RTL into the intermediate format and stores it into the specied or default library. Design (target, link, symbol and synthetic) libraries are also loaded at this stage. NOTE: While simulation-only constructs are treated as errors when analyzing the RTL model in the Design Analyzer, they are not when analyzed external to the Design Compiler/Analyzer (using gvan, vhdlan or Verilog XL), and hence can be used in simulation models and test benches.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help

C Command Window

analyze -format format hdl_le(s)


File Name(s): Directory: /home/... ../(Move up one directory) hdl_le1.v hdl_le2.v hdl_le3.vhd hdl_le4.vhd File Format: Library: DEFAULT WORK Create New Library if it Doesnt Exist OK Cancel 3. Select library Verilog 1. Select hdl_le design_analyzer> 2. Select format

Errors, Warnings, & Reports Error: File hdl_le could not be found in the search path ... - make sure the search path includes the directory where the source les are. To include the directory where you start Design Analyzer from, include a dot (.) as one of the components of the search path. - Unlike other stand-alone VHDL/Verilog compilers, you must specify the extension of the le (if the le has an extension) even when a le has a standard VHDL/Verilog extension of .vhd, .vhdl or .v Error: Could not read the following target | link | symbol | synthentic library: ... - Check that the library you have specied in the .synopsys_dc_setup le or using the Setup Defaults... is existent and readable and has its path included in the search path. Error: Depending on 2 edges of same variable clock_pin not supported ... - You cannot use both the positive and negative edges of the same clock variable in the same process or always block.

test.v(test.vhd) hdl_le(s) A list of VHDL or Verilog les. Note that Design analyzer does not automatically append the standard VHDL/Veriolg extensions (.vhd, .vhdl, .v), and therefore the le must be specied with its extension if it has one. WORK library The library where the analyzed les should be put. Normally, select the WORK or DEFAULT library, which is usually mapped to the directory where your design source les are. format The format of the HDL le. It is either verilog or VHDL. CLK clock_pin A variable used as a clock in the VHDL or Verilog design.

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4. Click

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4.4 Elaborate the Design


Elaborating builds the design from the intermediate format of a Verilog or VHDL model. The RTL model is converted into generic gates and logic blocks. Again, constructs not supported for synthesis (such as using both clock edges in a process or always block) are reported. The elaborate process also reports the memory elements (ip-ops and latches) and tristate-buffers implied in your design.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Library: DW01 DW02 WORK Design: module1(verilog) module2(verilog) entity1(arch) antity2(arch) Parameters: Re-Analyze Out-OfDate Libraries OK Cancel 4. Click Help 1. Select library

C Command Window

elaborate module (elaborate entity)


design_analyzer>

2. Select module(verilog) or entity(arch)

Errors, Warnings, & Reports Error: Clock variable clock_pin is being used as data in ... - clock_pin, used as a clock with the statements clock_pinevent and clock_pin = 1 (= 0) or posedge (negedge) clock_pin, cannot be used in the right-hand side of an assignment statement in the same process or always block. Use a separate process or always block to make this assignment. Error: This use of clock edge specication not supported in ... - You cannot use both the positive and negative clock edges of the same clock variable in the same process or always block. - In VHDL, you cannot use more than one clock_pinevent and clock_pin = 1 (= 0) clock statements in one process. If possible, make all assignments in one clock statement or use more than one process. Info: Inferred memory devices in process ... Info: Inferred THREE-STATE control devices in process ... - Always check this information about inferred devices to make sure that your RTL description does not imply unnecessary ip-ops (due to variable assignments in clock_pinevent and clock_pin = 1 (= 0) statements or always blocks with posedge (negedge) clock_pin statements), latches (due to variables not assigned to in all conditions of if and case statements - to aviod latches, also make the variable assignment in the else or default clauses of these statements), and tristate buffers.

test entity The entity name of the VHDL model. If the design contains more than one entity, elaborate each entity separately. behav arch The architecture of the VDHL entity. test module The module name of the Verilog model. If the design contains more than one module, elaborate each module separately. WORK library The library where the les were analyzed into. Normally, select the WORK or DEFAULT library, which is usually mapped to the directory where your design source les are. CLK clock_pin A variable used as a clock in the VHDL or Verilog model.

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3. Turn ON

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4.5 Specify Clock Constraints


Design and timing constraints must be set prior to compiling (mapping) the design. Constraints for clocks include the period (in units specied in the technology le - usually ns), skew type (either ideal clock network or that in which the clock delays due to the propagation delay through the clock network), whether hold time violations should be corrected (xed) by inserting delays, etc. It is necessary to specify the clock period if you want to estimate the speed of the design (setup and hold violations) using the static timing analyzer (Design Time) after you have compiled the design.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints O1 Optimization Directives O2 Clock Name: Clock Port: Specify... Skew... Help

C Command Window

CLK I1 I2 T 1. Select clk_pin


create_clock -period period cck_pin x_hold clk_pin set_clock_skew -skew_type clk_pin


design_analyzer>

2. Type period

Errors, Warnings, & Reports


0.0 Period: 25.0 Edge: Skew... Dont Touch Network Apply Fix Hold Cancel 50.0

3. Turn ON

4. Click

Clock Name: Clock Delay Type Ideal Rise: Propagated Uncertainity Min: Max: Fall: Same Rise and Fall

5. Click

6. Swith ON skew_type

7. Click

Same Min and Max Apply Cancel 8. Click 9. Click

CLK clk_pin Pin or port on which clock constraints are to be set. 20 period The period of the clock. Only the number should be specied - the units (usually ns) are specied in the technology le. propagated skew_type Species the type of clock network. It is either ideal (an ideal clock network with no skew) or propagated (the clock skew depending on the propagation delays through the network). The default is ideal.

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4.6 Set Test Methodology and Scan Test Style


Synopsys Test Compiler can automatically insert boundary scan and/or scan test circuitry into your design. This manual covers scan test design only. The two scan test methodologies are full scan test and partial scan test. In full scan test, all sequential elements in the design are replaced by their scannable equivalents, where as in partial scan test, a constraint-driven scan selection algorithm is used to select optimal cells to scan. Partial scan therefore has less performance and area costs than full scan, but has a lower fault coverage than the later. There are several styles of scan-test implementation. Multiplexed ip-op scan test design is the most commonly supported scan test style. In this implementation, the input to a ip op is multiplexed between the normal circuit data and the scan test. The other scan styles are described briey in Appendix A.1. NOTE: For menu-driven execution, test methodology is set later when the test circuitry is just about to be inserted.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives
T

C Command Window Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...

set_test_methodology test_methodology set_scan_style scan_style


design_analyzer>

Design Name: Ungroup Boundary Optimization Sequential Elements: Port is Pad: Test Scan Style:

Errors, Warnings, & Reports


Dont Touch Disable Wired Logic (E Latch...

Structured Logic Apply Timing Driven Structuring Apply Boolean Optimization Apply Cancel

3. Click

full_scan test_methodology The test methodolgy to be used. It is either full_scan or partial_scan. The default is full_scan. multiplexed_ip_op scan_style Denes the scan-test implementation. It is either multiplexed_ip_op, lssd, aux_clock_lssd, clocked_scan, combinational or none. See Appendix A.1 for details.

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Flip Flop...

Design Pad Attributes... None 1. Select scan_style

Flatten Logic Flatten Effort: Flatten Minimize: Flatten Phase: Low Medium High Single Output Multiple Output None Dont Apply Apply Strategy

2. Click

4.7 Set Other Design Constraints


Apart from clock and test constraints, there are a number of other attributes that you might need to set before compiling your design. The Synopsys Command Reference Manual lists all the available attributes. However, in most cases, the default settings of most attributes sufce. A few common design constraints that need to be set include: Maximum Fanout: sets the maximum fanout for driving pins (default value can be set for the library) Maximum Transition Time: The maximum time required for driving pins to change logic values. Speed vs. Area: whether timing is critical in the design when compared to area. NOTE: for command-line execution, the timing-is-critical attribute is set later with the compile command.

C Synopsys Design Analyzer Setup File Edit View Design Constraints... Timing Constraints... Derive... Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives Help

C Command Window

set_max_fanout max_fanout design set_max_transition max_trans design


design_analyzer>

1. Type max_fanout

Design Name: Optimization Constraints: Max Area: Max Power: Design Rules: Max Fanout: Max Transition: Test Constraints: Min Fault Coverage: Area Critical Apply 4. Click 5. Click 95% Cancel

Errors, Warnings, & Reports

10 max_fanout The value of the maximum fanout. 2.0 max_trans The maximum transition time. Only the number should be specied, but its units must be consistent with those specied in the technology library (usually ns). test design Name of the design (entity name or module name)

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2. Type max_trans

3. Turn ON

Timing Critical

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4.8 Compile the Design


This step performs logic and gate-level synthesis and optimization. The result is a netlist (and a schematic) of the design using the cells in the target library. During optimization, the Design Compiler tries to meet the user-specied design constraints.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T

C Command Window

compile -map_effort map_effort

design_analyzer> 1. Turn ON Map Design Map Effort: 2. Turn ON map_effort Low Medium High

Errors, Warnings, & Reports

More Map Options... Verify Design Map Effort:

Low

Medium

High

3. Turn ON

Allow Boundary Optimization Execute in: Foreground Background Cancel

4. Click

OK

medium map_effort Species how much effort and time should be spent by the processor on mapping. Valid settings are Low, Medium and High. High effort yields a better optimized circuit, but the CPU time taken to achieve this might be too much for very large designs. The default map effort is Medium.

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4.9 Check the Design Rules


This checks the current design for problems. All errors must be corrected. While most warnings can be ignored, it is necessary to check each one of them since some warnings might actually indicate errors in the logic of the design.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Link Design... Check Design... Time Design Show Timing... Show Net Load... Highlight Test Report... Report... Help

C Command Window

check_design

design_analyzer>

Errors, Warnings, & Reports


Options Exclude Warnings Summarize Warnings Detailed Warnings Options 2. Turn ON Check Current Level Check All Levels Check Timing OK Cancel

test design The name of the design you are currently checking. port_name The name of any port on your design.

From RTL Description to Layout

1. Turn ON

3. Click

Warning: In design design port port_name is not connected to any nets. - Make sure that the port port_name is intentionally not associated with any logic in your HDL description. Otherwise if the port is included for future expansion of the design, or for component interface consistency, the warning may be ignored.

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4.10 Check the Test Design Rules


This checks the design against the design rules of the selected scan test methodology and scan style. This must be done prior to inserting scan test circuitry and generating test patterns. Again, while it is not necessary to correct warnings, it must be remembered that violations resulting in these warnings will usually reduce the fault coverage. NOTE: For menu-driven execution, the test_methodology and scan_style must be set to values set in Step 4.6.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...

C Command Window

check_test

1. Turn ON test_methodology
T

design_analyzer> Methodology: 2. Select scan_style Scan Style: Full Scan Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules Verbose

3. Click

Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager...

4. Click

Format Vectors... Display Reports... Cancel

full_scan test_methodology The test methodolgy to be used. It is either full_scan or partial_scan. The default is full_scan. multiplexed_ip_op scan_style Denes the scan test implementation. It is either multiplexed_ip_op, lssd, aux_clock_lssd, clocked_scan, combinational or none. See Appendix A.1 for details..

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4.11 Estimate Test Fault Coverage


At this point, you can optionally estimate the test fault coverage by running automatic test pattern generation (ATPG) on the design. This is especially important if you had warnings when running check test design rules in Step 4.10. By running ATPG at this point, you get an idea of the effect that the warnings (usually uncontrollable pins) have on the fault coverage. You can then decide whether to correct the warnings or not. Appendix A.1 lists some common test design rule violations and how they can be corrected.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window

create_test_patterns

design_analyzer> Methodology: Scan Style: Full Scan Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports Warning: Design has no scan path. Generated vectors will not be saved. - Ignore this warning. It simply reminds you that you have run ATPG before inserting scan test circuitry. ATPG will be run again later.

Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... 2. Click Test Manager... Format Vectors... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Display Reports... Cancel Verbose

Restore/Delete Test Program... Cancel

5. Click

design.vdb Compact Patterns Efoort: Low (Backward) Contention Check Float Check Additional Options...

4. Click

3. Click

Execute in: Foreground OK

Background Cancel

From RTL Description to Layout

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Initial File: Output Pattern File:

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Analyze Fault Coverage...

4.12 Perform Area and Timing Analysis


If you want to see the effect that scan insertion has on the area and performance of the design, you must analyze the design for area and timing before and after scan test insertion. You can then decide whether to incrementally optimize the design to try and meet the performance and area of the design without scan, or to change the test strategy all together.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Link Design... Check Design... Time Design Show Timing... Show Net Load... Highlight Test Report... Report... Help

C Command Window

report_area report_constraints report_timing


design_analyzer>

Errors, Warnings, & Reports


Attribute Reports Compile Options All Attributes Design Bussing FSM Cell Net Clocks

1. Turn ON Area Clock Skew Clock Tree Constraints

2. Turn ON

3. Turn ON

From RTL Description to Layout

Path Groups Port Resource

Analysis Reports Cross Ref. Hierarchy Point Timing Power

Report: In the contraints report, note the (MET) and (VIOLATED) against each of the design constraints set earlier. - This shows that the design constraint has either been met or violated by the indicated value. Report: In the timing report, note the slack (MET) at the end of the report. - This indicates the time that the longest path in the design settles before the clock changes. A negative value indicates a violation. Increase the clock period or reoptimize the design if there is a slack violation.

Reference Selected Timing Timing Requ

Set Options... Send Output To: Window

Clear Choices File

4. Click

File: Apply 5. Click Cancel

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4.13 Insert Scan Test Circuitry


This step adds test circuitry to the design. Basically, all sequential cells (ip-ops and latches) are replaced by their scannable versions and/or logic is added to multiplex between scan test serial shifting and normal circuit operation. Pins for scan test enable (test_se) and scan test shift input (test_si) are also added to the design. By default, Test Compiler also adds logic to disable internal three-state bus drivers to ensure that only one driver drives the bus at a time. Since this will more likely have already been incorporated in your design (otherwise chances are that you have an erroneous design with bus contention), you must prevent Test Compiler from adding this disabling logic by running test insertion with the no_disable option.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window

insert_test -no_disable

design_analyzer> Methodology: Scan Style: Full Scan Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports Warning: Deleting current test program test_program_name because it is not consistent with the current design. - Again, ignore this warning. It refers to the ATPG that was run in step 6.11. Since the design has changed, the next ATPG will use a new initial fault list.

2. Turn OFF

3. Click

Execute in: Foreground OK

Background Cancel

test.vdb test_program The test program that was created with the last ATPG run and is currently being deleted.

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Maximum Scan Chain Length: Number of Scan Chains:

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Contains Existing Scan Circuitry Check Design Rules Verbose

Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager... 1. Click Format Vectors... Display Reports... Cancel

4. Click Insert Scan Options: Insert Test Cells Route Scan Path Disable Internal Three-State Drivers

4.14 Optimize the Scan Design


Now that scan circuitry has been added, it is possible that some design constraints, which were originally met, will now be violated. Obviously, the scan circuitry has added extra area. It is therefore very important to re-run the area and timing analysis as was done in Step 4.12. If there are timing violations, or if you simply want to further optimize the design area and timing, you must now run an incremental compilation. Incremental compilation uses the existing compiled gate-level design to improve the design constraints. If no improvements can be made, the design is left unchanged. After running incremental optimization, you must once again run area and timing analysis (Step 4.12) to check if the design now meets all the design constraints. If the design does not meet timing constraints even after several optimizations and/or redesign, you may wish to consider increasing the clock period and/or relaxing some of the timing constraints.

Step 6.12 (Area and Timing Analysis)


C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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Step 6.12 (Area and Timing Analysis)


C Command Window

compile -incremental_mapping

design_analyzer> Map Design Map Effort:

Low

Medium

High

OK

3. Click

Step 6.12 (Area and Timing Analysis)

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Incremental Mapping Prioritize Min Paths Map in Place

4. Click

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OK

Cancel

More Map Options... 1. Click Verify Design Map Effort:

Step 6.12 (Area and Timing Analysis) Errors, Warnings, & Reports

Low

Medium

High

Allow Boundary Optimization 2. Turn ON Execute in: Foreground Background

4.15 Check Test Design Rules & Report Scan Path


Again, check the test design rules as outlined in Step 4.10. If there are no violations, you now need to know which ports of the design are used for scan test. The input ports test_se and test_si have been added by the Test Compiler specically for scan test. However, Test Compiler multiplexes one of the design output ports to be used as a scan output port during scan test. It is necessary to nd out which port is used as the scan output in order to dene it correctly when you set up the chip pins for scan test (Step 4.23). Apart from the scan ports, you can also optionally report the actual scan chain (cells in the scan path).

Step 4.10 (Check Test Design Rules)


C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window

check_test report_test -scan_path -port


design_analyzer>

Methodology: Scan Style:

Full Scan

Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules 1. Turn ON Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager... Format Vectors... Display Reports... Verbose

7. Click 3. Turn ON

Send Output To: 5. Click File: Apply

Window

File

Cancel

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4. Turn ON

JTAG Assertions Methodology ATPG Conicts Ports Constraints Scan Path Coverage Dont Fault Faults Fault Options: Untested

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2. Click

Cancel

4.16 Save the Core Design


You may now save the design in the Synopsys internal database (DB) format. This is important if you wish to stop at this stage and continue the design process later. The saved db le will allow you to read in the synthesized gate-level design without having to compile it again from the RTL model. The save command outlined here will save all the designs in the hierarchy in a le named design.db, where design is the name of the top-level entity (VHDL) or top-level module (Verilog). To save the design using a different name or a different format, or to save the top-level without the other designs in the hierarchy, use the Save As... command as outlined in Step 4.25. If you decide to use the Save As... command for this step, make sure that you select the DB (Synopsys internal database) format and save all the designs in the hierarchy. You may however use a different le name than the default.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help

C Command Window

write -format db -hierarchy

design_analyzer>

Errors, Warnings, & Reports

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4.17 Generate the Chip RTL Model (Verilog)


The core design just completed does not have pads. To insert pads, you must write an RTL model of the chip with an instantiation of the core design. There are two reasons why it is advisable to use this approach. Firstly, scan insertion has to be done on the core design, without the pads, and then routed to the pads later. Secondly, in order for Synopsys Design Compiler to automatically insert the pads, the RTL code must imply the type of pads available in the technology library. While there are almost no problems with input pads (Design Compiler will automatically insert an input pad for each input port on the top-level design), Design Compiler will issue an error (Error: No matching pad found for port...) if the RTL code, say, implies a standard output pad but the library only contains pads with output enable (three-state) control pin and vice versa. Therefore, this step has a very high potential of being technologydependent. However, it must be noted that in most technologies, output pads fall into two categories: those with output enable pins, and those without. Therefore, you can write RTL code to imply one type of pad and if Design Compiler issues an error, change the code to imply the other type. The most common type of output pad is one with output enable pin (These are the pads available in Mitel 1.5 m and Nortel 0.8 m BiCMOS technologies). Therefore, rst write your RTL code to imply this pad type.

For illustration purposes, assume that the core RTL model has the ports input I; output O1; output [3:0] O2; Suggested names for chip Verilog le and module are designchip.v and designchip, respectively. In both the chip module and the core component instantiation, include all the ports in the core Verilog model, and also add the following two ports :
input test_si, test_se;

TUTORIAL STEP

module testchip (test_si, test_se, RST, CLK, ACI, ACO); input test_si, test_se; input RST, CLK; input [2:0] ACI; output [2:0] ACO; test c_core (.test_si(test_si), .test_se(test_se), .RST(RST), .CLK(CLK), .ACI(ACI), .ACO(ACO)); endmodule;

For pads with output enables, - Declare a variable to control the output enable:
reg pads_oe;

- Declare an internal variable for each core output port:


reg O1_i; reg [3:0] O2_i;

- Write an always block to control the output pads:


always @(pads_oe or O1_i or O2_i) begin if (pads_oe == 1b1) begin O1 = O1_i; O2 = O2_i; end else begin O1 = 1bZ; O2 <=4bZ; end pads_oe = 1b1; end

For pads with output enable, instatiate the core as:


design c_core port map (.test_si(test_si), .test_se(test_se), .I(I), .O1(O1_i), .O2(O2_i))

For pads without output enable, instatiate the core as:


design c_core port map (.test_si(test_si), .test_se(test_se), .I(I), .O1(O1), .O2(O2))

test design the core design module name

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4.18 Generate the Chip RTL Model (VHDL)


The core design just completed does not have pads. To insert pads, you must write an RTL model of the chip with an instantiation of the core design. There are two reasons why it is advisable to use this approach. Firstly, scan insertion has to be done on the core design, without the pads, and then routed to the pads later. Secondly, in order for Synopsys Design Compiler to automatically insert the pads, the RTL code must imply the type of pads available in the technology library. While there are almost no problems with input pads (Design Compiler will automatically insert an input pad for each input port on the top-level design), Design Compiler will issue an error (Error: No matching pad found for port...) if the RTL code, say, implies a standard output pad but the library only contains pads with output enable (three-state) control pin and vice versa. Therefore, this step has a very high potential of being technologydependent. However, it must be noted that in most technologies, output pads fall into two categories: those with output enable pins, and those without. Therefore, you can write RTL code to imply one type of pad and if Design Compiler issues an error, change the code to imply the other type. The most common type of output pad is one with output enable pin (These are the pads available in the Mitel 1.5 m and Nortel 0.8 m BiCMOS technologies). Therefore, rst write your RTL code to imply this type of pad.

For illustration purposes, assume that the core RTL model has the ports I: in std_logic; O1: out std_logic; O2: out std_logic_vector(3 downto 0); Suggested names for chip VHDL le and entity are designchip.vhd and designchip, respectively. In both the chip entity and the core component declaration, include all the ports in the core RTL model, and also add the following two ports :
test_si: in std_logic; test_se: in std_logic;

TUTORIAL STEP

entity testchip is port ( test_si, test_se: in std_logic; RST, CLK: in std_logic; ACI: in std_logic_vector (2 downto 0); ACO: out std_logic_vector (2 downto 0)); end testchip; architecture behav of testchip is

For pads with output enables, - Declare a signal to control the output enable:
signal pads_oe : std_logic;

- Declare an internal signal for each core output port:


signal O1_i: std_logic; signal O2_i: std_logic_vector(3 downto 0);

- Write a process to control the output pads:


PadsProcess: process (pads_oe, O1_i, O2_i) begin if (pads_oe = 1) then O1 <= O1_i; O2 <= O2_i; else O1 <= Z; O2 <= ZZZZ; end if; end process PadsProcess; pads_oe <= 1;

component test port ( test_si, test_se: in std_logic; RST, CLK: in std_logic; ACI: in std_logic_vector (2 downto 0); ACO: out std_logic_vector (2 downto 0)); end component; begin c_core: test port map (test_si=>test_si, test_se=>test_se, RST=>RST, CLK=>CLK, ACI=>ACI, ACO=>ACO); end behav;

For pads with output enable, instatiate the core as:


c_core: design port map (test_si=>test_si, test_se=>test_se, I=>I, O1=>O1_i, O2=>O2_i)

For pads without output enable, instatiate the core as:


c_core: design port map (test_si=>test_si, test_se=>test_se, I=>I, O1=>O1, O2=>O2)

test design the core design entity name

From RTL Description to Layout

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4.19 Analyze, Elaborate and Constrain the Chip


Analyze the chip RTL model (Step 4.3), and elaborate it (Step 4.4). Then set the design constraints; this might include specifying the clock (Step 4.5), test constraints (Step 4.7) and other design constraints (Step 4.6). NOTE that since the core design already contains scan circuitry (and you are not adding any new scan circuitry on the chip design), you must include the -existing_scan option (or when using menus, turn ON the Contains Existing Scan Circuitry button) when you specify the scan methodology.

Step 4.3 (Analyze the chip hdl_le)1 Step 4.4 (Elaborate the chip entity or module)2 Step 4.5 - Step 4.7 (Constrain the chip design)3

Errors, Warnings, & Reports

1hdl_le

test_chip.v (test_chip.vhd)

For the Analyze command hdl_le(s), select/specify the chip HDL le you created in Step 4.17/Step 4.18. Do not specify the core design HDL le. All other information is the same as for the previous (core design) Analyze command execution.
2entity/module

test_chip For the Elaborate command entity or module, select the select/specify the entity or module name of thechip HDL model created in Step 4.17/Step 4.18. Do not specify the core deisgn entity or module. If you use a different architecture name for the chip design, remember to specify it, otherwise all the other information is the same as that when you executed athe Elaborate command for the core design.

3For

command-line execution, when you run the set_test_methodology command, remember to run it wih the option -exisiting_scan to tell Design/Test Compiler that the design already contains scan circuitry. For example, to set test methodolody to full scan, run the command as follows: set_test_methodology full_scan -existing_scan

Other constraints should be set as for the core design.

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4.20 Set Dont Touch Attribute on the Core


Since the core design is already optimized, you must set a dont_touch attribute on the core instance in order to prevent Design Compiler from trying to re-optimize the design. All logic necessary for pad insertion is thus external to the core. This makes debugging easier, and also ensures that most of the analysis done earlier on the core are not invalidated with insertion of extra logic into the core design.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives CLK I1 I2 O1 O2 Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...

C Command Window

set_dont_touch instance_name

2. Select
T

design_analyzer>

1. Click

Errors, Warnings, & Reports


Cell Name: instance_name Referencing: cell_design_name Compile Attributes: Ungroup Cells Hierarchy Dont Touch Allow Boundary Optimization Sequential Elements: Max Time Borrow: 4. Click Scan Replacement: Apply Always Never Cancel Flip Flop... Latch...

3. Turn ON

5. Click

c_core instance_name The name of the instance of the core design in the chip. Note that this is not the design (entity or module) name of the core, but rather the name of the instance or component when it is instantiated in the chip design.

From RTL Description to Layout

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4.21 Set Pad Attributes


In order for a pad to be inserted on a design port, the port must be specied as a pad using the set_port_is_pad attribute. Other pad attributes, such as... may also be specied before the actual pad insertion process.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives
T

C Command Window Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...

set_port_is_pad *

design_analyzer>

Design Name: Ungroup Boundary Optimization Sequential Elements: Port is Pad: Test Scan Style:

Errors, Warnings, & Reports


Dont Touch Disable Wired Logic (E Latch... 1. Turn ON

Flip Flop...

Design Pad Attributes... None

Flatten Logic Flatten Effort: Flatten Minimize: Flatten Phase: Low Medium High Single Output Multiple Output None Dont Apply Apply Strategy 2. Click

Structured Logic Apply Timing Driven Structuring Apply Boolean Optimization Apply Cancel

3. Click

From RTL Description to Layout

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4.22 Insert Pads & Optimize the Design


This step will physically insert pads on all the ports that have been set up for pad insertion in Step 4.21 and optimize the design. Pads must be inserted before the design is compiled. Also since the core design has already been optimized, only incremental compilation (Step 4.14) is necessary.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Delete Insert Pads... Select... Unselect All Group... Ungroup... Uniquify Reset... Help

C Command Window

insert_pads compile -incremental_compilation


design_analyzer>

Errors, Warnings, & Reports


Verify Results Effort: Set Pad Type 1. Click Low Medium High

Design Pad Attributes...

Port Pad Attributes... OK Cancel

Step 4.14 (Incremental Compilation)

From RTL Description to Layout

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4.23 Dene the Chip Scan Input Pins


To route the core design scan circuitry to the chip pads, you must specify the chip pins that are to be used as scan pins (scan enable, scan input, and scan output). The scan input pins are test_se and test_si.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...

C Command Window

set_signal_type test_scan_enable test_se set_signal_type test_scan_in test_si


design_analyzer>

2. Select Pin test_se


T

1. Click

CLK I1 I2 test_se test_si

O1 O2

Errors, Warnings, & Reports

Port Name:

selected_port

Maximum Fanout: Maximum Transition: Port is Pad: Connected to: Set Equal... Test Hold: Signal Type: Apply Port Pad Attributes... Logic 0 Logic 1

Set Opposite... None Scan Enable Cancel 8. Click 7. Click

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3. Select Test Scan Enable 5. Select Pin test_si 6. Select Test Scan In

4. Click

4.24 Dene the Chip Scan Output Pin


As mentioned earlier, Test Compiler multiplexes one of design output pin to be used as the output pin during scan shift. This pin was reported in Step 4.15. You should now congure it as the chip scan output pin.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Clocks Operating Environment Optimization Constraints Optimization Directives CLK I1 I2 test_se test_si Help Design... Input Port... Output Port... Cell... Pin... Net... Timing Paths...

C Command Window

set_signal_type test_scan_out scan_out

1. Select Pin scan_out


T

design_analyzer>

O1 O2

Errors, Warnings, & Reports

Apply 4. Click

Cancel

O scan_out The design output pin that is also used (multiplexed) as a scan output pin. This pin was reported in Step 4.15 when you run the report_test command.

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2. Select Test Scan Out Port Name: selected_port

Maximum Transition: Port is Pad: Unonnected 3. Click Signal Type: Scan Out Port Pad Attributes...

4.25 Check Test, Report Scan Path & Save Design


Pad insertion may sometimes introduce additional test design rule violations. You must therefore once again run check test before you save the nal design. You can also, optionally, report the scan chain and scan ports to make sure that the core design scan circuitry is correctly routed to the chip pins.

Step 4.15 (Check Test Rules & Report Scan)


C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help C Command Window

report_test -scan_path -port write -format db -hierarchy


design_analyzer>

Errors, Warnings, & Reports

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4.26 Save the Design in HDL and Export Formats


So far the design has been saved in the Synopsys internal database format (db). But in order to export the design to third part tools for placement and routing, the design has to be saved in a format other than db. Also, to simulate the gate-level design (Step 5), the design must be saved in the required HDL format. The saved HDL design is simply a structural hierarchical HDL code with the lowest level consisting of the interconnections of the technology library components as they appear in the schematic. Therefore, you must now save the design twice, rstly in Verilog or VHDL format (for simulation), and then in the format required by the third party tool (e.g. EDIF to import a Nortel 0.8 um BiCMOS design to Cadence, Verilog to import a Mitel 1.5 um design to Cadence, XNF to import a Xilinx design to the XACT tools).

Perform this step twice: rst for the HDL format (e.g. verilog), and then for the export format (e.g. edif)
C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Read... Analyze... Elaborate... Import Save Save As... Save Info Plot... Quit Help 1. Type le_name or 1. Select le_name C Command Window

File Name: Directory: /home/... ../(Move up one directory) le1 le2 le3 le4 File Format: DB

write -format le_format -hierarchy -output le_name


design_analyzer>

2. Select le_format

test_g.v le_name The name of the le that the design has to be saved as. When saving the HDL gate-level le, make sure that you specify a different le name from the one containing behavioral design. verilog le_format The format in which you want the design to be saved. Valid formats are: db Synopsys internal database format vhdl IEEE Standard VHDL verilog Cadence Verilog HDL edif Electronic Design Interchange Format xnf Xilinx Netlist Format mif Mentor Interchange Format (MIF) equation Synopsys equation format st Synopsys State Table format tegas Tegas design Language netlist Fornat lsi LSI Logic Corporation Netlist Format pla Berkeley (Espresso) PLA format

From RTL Description to Layout

Errors, Warnings, & Reports

Save All Designs in Hierarchy OK Cancel

3. Turn ON

4. Click

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4.27 Specify Test Timing Parameters


A few timing parameters need to be set prior to generating test vectors (ATPG) and running fault simulation (TestSim). The most common ones include the test defaut delay and strobe times, as well as the timing parameters of the test clock. These are briey described below: test_default_delay For ATPG, this value denes the time at which values are applied to the primary inputs. Its value must be less than both the output strobe time and the capture clock edge value. The value set for test_default_delay is used by the check_test command when checking the design against the design rules of the scan test methodology. It is also used by the write_test command when producing a test program. For TestSim, the value of test_default_delay denes the default input delay for primary inputs, and must be set to the value that was used when generating the vectors being input to TestSim. It must be less than the clock period. test_default_strobe This denes the default time at which values are strobed at the primary outputs and bidirectional ports. Its value must be less than the clock period. test_default_strobe also affests both the check_test and write_test commands. test clock parameters This includes the period, waveform and default period of the clock to be used during test.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help

C Command Window

test_default_period = default_period test_default_delay = default_delay test_default_strobe = default_strobe create_test_clock clock_pin -period period -waveform {rise_edge fall_edge}

design_analyzer>

CLK clock_pin Pin to be used as clock during test. 100 period Value of the period of the test clock in ns.

45 55 rise_edge fall_edge Rise and fall edge times of the test clock over one period (typically, the rst edges after time zero).

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95 default_strobe Value of the default test strobe time in ns.

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Errors, Warnings, & Reports

4.28 Generate Test Vectors


In this step, Test Compiler uses the ATPG to generate a minimal set of scan test vectors to test your design for all possible stack-at faults. The fault coverage achieved by these test vectors, plus the number of detected and undetected (untested) faults is also reported.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window

create_test_patterns -compaction_effort low

design_analyzer> Methodology: Scan Style: Full Scan Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... 2. Click Test Manager... Format Vectors... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel Test Pattern Generation Options: Use Initial Pattern File: Display Reports... Cancel Verbose

5. Click

Compact Patterns Efoort: Low (Backward) Contention Check Float Check Additional Options...

3. Click

Background Cancel

OK

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4.29 Analyze Fault Coverage


It is important to analyze the fault coverage and obtain a detailed report especially for untested faults (you can also report on faults that are redundant, oscillating, etc.). Faults may be untested because of design rule violations (such as combinational feedback loops and gated clocks), xed logic levels at nodes (if you used the x_test_hold command) or faults with unpredictable effects (such as faults on enable pins of three-state bus drivers may cause bus contention).

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
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C Command Window

report_test -coverage -faults -class untested

design_analyzer> Methodology: Scan Style: Full Scan Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... 2. Click Test Manager... Format Vectors... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel Mask Faults Methodology Ports Scan Path Timing (TestSim) Display Reports... Cancel Verbose

3. Turn ON

Coverage Faults Fault Options: Untested Report Scope: All (Cumulative) Send Output To: File: Last (Incremental) Window File

4. Type untested

5. Click 6. Click

Apply

Cancel

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Assertions ATPG Conicts Constraints Dont Fault JTAG

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4.30 Format Test Vectors


Now you have to format the test patterns into manufacturing test vectors that can be used on a specic tester or simulator. Basically, there are four types of vector formats: Simulation (VHDL or Verilog), Intermediate (TDS ASCII or WGL), ASIC, and Synopsys. For simulation, the test vectors are formatted as test benches, with serial or parallel load of the scan chain. For VHDL, to speed up the simulation, the ASCII vectors can be separated from the test bench by selecting the TEXTIO option. Intermediate formats are provided by the Summit Design Software, which can translate these vectors to formats required by various Automatic Test Equipment (ATE) systems. ASIC format uses a proprietary Custom Test Vector (CTV) format for a specic supported ASIC vendor (such as LSI Logic, Mitsubishi, Motorola, Texas Instruments and Toshiba). Vectors in Synopsys format can be used by the Test Compiler to translate the vectors into your required format.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T

C Command Window

write_test -format vector_format -parallel1

design_analyzer> Methodology: Scan Style: Full Scan Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules Verbose

Insert Internal Scan Circuitry... Insert Boundary (JTAG) Scan Circuitry... Test Manager... Format Vectors... Display Reports... Cancel Input Pattern File: Output File: Format: design.vdb design Parallel 3. Optionally1 Turn ON/OFF 1. Click

5. Click

synopsys

wgl vector_format One of the following supported vector formats: vhdl, verilog, wgl (TSSI WGL), tds (TSSI TDS ASCII), synopsys (Synopsys generic), mif (Mentor Interchange Format (MIF)), pla (Berkeley (Espresso) PLA format).
1-parallel

Use this option only with VHDL or Verilog formats.

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Cancel

an

Only Format Current Test Program Format Entire Test Program Sequence

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4.31 Generate TestSim (Fault Simulation) Libraries


Synopsys comes with a TestSim fault simulator that can be used to fault simulate the ATPG vectors generated in the previous steps. But before you can perform fault simulation, you must generate TestSim libraries (using write_test_lib command) for all the libraries specied in the link_library variable. You must also create a TestSim model of your design. NOTE: In most cases, the technology libraries and symbol libraries have the same names. Therefore, in order to imply a unique library when specifying the library name in write_testsim_lib, you must rst remove from memory (using free command) all symbol libraries that have the same names as the libraries specied in the link_library, then run write_testsim_lib command on all link libraries, and nally read back into memory all the symbol libraries you removed earlier.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help

C Command Window

free symbol_library write_testsim_lib link_library read symbol_library create_testsim_model design_chip_testsim.db

design_analyzer>

Errors, Warnings, & Reports

test design The root name of your design.

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hcells link_library A technology library specied in the link_library variable. If there are more than one library specied, run the write_testsim_lib command on each library, one at a time.

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hcells.sdb symbol_library The le of the symbol library that have the same root name with one of the link libraries. Run the free command on all such symbol libraries before running the next command.

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4.32 Fault Simulate ATPG Vectors in Parallel Mode


Simulating the ATPG vectors in parallel-load format means that the scan chains are loaded by forcing data directly onto the scan input net of each scan cell and then applying the test clock to load the scan input nets. Captured values are measured directly from the scan output nets after the parallel capture cycle has occurred. Simulation time is thus proportional only to the number of scan patterns being simulated. This leads to signicant decrease in the simulation run time when compared to serial-load format in which simulation time is proportional to both the number of test patterns as well as the length of the longest scan chain.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T

C Command Window

fault_simulate -input design_chip.vdb -format vdb -output parallel -use_testsim_model design_chip_testsim.db


design_analyzer>

Methodology: Scan Style:

Full Scan

Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... 2. Click Insert Boundary (JTAG) Scan Circuitry... Test Manager... Verbose

Display Reports... Cancel

Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel 9. Click 3. Type design_chip.vdb

10.Click Pre Fault Simulation Check: Verify Timing Parameters Fault Simulation Context: Input Vectore File: Input Format: Output Test Program: Save TestSim Model File: Use TestSim Model File: Signal Defn. (SDF) File: On Off Stuck-at Faults: Mode: Evaluate Probables Normal On Off IDDQ Defects: IDDQ Defect Model: Node Toggle Transistor Shorts Maximum Measurements: Incremental Coverage %: OK 8. Click vdb

4. Select vdb (Native TC)

5. Turn ON

6. Type parallel

7. Type design_chip_testsim.db

Cancel

test design The root name of your design.

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Multi-pass Test Generation ? Yes No

Format Vectors...

4.33 Compare TestSim & Test Compiler Fault Coverage


In this step, you analyze the fault coverage produced by the TestSim (parallel-load) and then compare it to that produced by Test Compiler. Therefore after analyzing the TestSim fault coverage (and recording the results), you must restore the test status to the state after ATPG, and then analyze fault coverage again and record the results.

Step 4.29 (Analyze Fault Coverage)


C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T

C Command Window

report_test -coverage -faults -class untested restore_test design_chip.vdb report_test -coverage -faults -class untested
design_analyzer>

Methodology: Scan Style:

Full Scan

Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... 2. Click Insert Boundary (JTAG) Scan Circuitry... Test Manager... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel 7. Click 3. Turn ON Restore Test Program Name: delete Current Test Program Apply Cancel 8. Click Format Vectors... Display Reports... Cancel Verbose

4. Type design_chip.vdb

5. Click 6. Click

Step 4.29 (Analyze Fault Coverage)

test design The root name of your design.

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4.34 Fault Simulate ATPG Vectors in Serial Mode


As mentioned earlier, the serial-load format requires longer simulation time and larger disk space than parallel-load because the scan cells are loaded by applying data to the scan input ports and results are measured at the scan output ports, thus requiring a clock cycle to load/compare each bit in the scan chain. However, unlike parallel-load simulations which verify only the normal operation (parallel) cycles of the scan patterns, serial-load simulations verify both the scan shift and the normal operation as is the case on ATE systems. Therefore, if the number of scan patterns is small, or if you want to simulate the scan-check testbench, use serial-load simulation, otherwise for a large number of test patterns, use parallel-load. Serial fault simulation can only be used on multiplexed ip op scan style, and requires that vectors be in the TSSI TDS ASCII or TSSI WGL format.

C Synopsys Design Analyzer Setup File Edit View Attributes Analysis Tools Help Design Optimization... Finite State Machines... FPGA Compiler... Test Synthesis...
T

C Command Window

fault_simulate -input design_chip_0.WGL format wgl -output serial


design_analyzer>

Methodology: Scan Style:

Full Scan

Partial Scan

Multiplexed Flip Flop

Errors, Warnings, & Reports

Contains Existing Scan Circuitry Check Design Rules 1. Click Insert Internal Scan Circuitry... 2. Click Insert Boundary (JTAG) Scan Circuitry... Test Manager... Multi-pass Test Generation ? Yes No Create Test Patterns... Fault Simulate... Analyze Fault Coverage... Restore/Delete Test Program... Cancel 9. Click 3. Type design_chip_0.WGL Format Vectors... Display Reports... Verbose

10.Click Pre Fault Simulation Check: Verify Timing Parameters Fault Simulation Context: Input Vectore File: Input Format: Output Test Program: Save TestSim Model File: Use TestSim Model File: Signal Defn. (SDF) File: On Off Stuck-at Faults: Mode: Evaluate Probables Normal On Off IDDQ Defects: IDDQ Defect Model: Node Toggle Transistor Shorts Maximum Measurements: Incremental Coverage %: OK 8. Click wgl

4. Select wgl

5. Turn ON

6. Type serial

7. Type design_chip_testsim.db

Cancel

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test design The root name of your design. CLK clock_pin Pin to be used as the test clock.

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Cancel

5
Simulate the Gate-Level HDL Netlist
Verify the Functionality and Timing of the Synthesized Circuit
a b clk d q c clk b o

After synthesizing the circuit, it is important that you run the simulation on the resulting circuit in order to verify that the design still meets the intended functionality and timing. The simulation is run similarly to the way it was done for behavioral simulation (Section 4/5), except that now you make use of the timing models of the gates in the target library.

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5.1 Setup the Test Bench for Gate-Level Simulation


Since the HDL netlist of the synthesized circuit consists of target library gates, you need to specify the library as directory where the simulation models of these gates are. Also, you need to set the test bench simulation time scale to conform with the time scale specied in these simulation models. To do this, add the following lines in your test bench:

TUTORIAL STEP

dene library_name dir=sim_model_dir uselib library_name timescale unit_time/resolution_time where, library_name The name you choose to give the library. Again, this doesnt have to be the same name as the actual name of the library - it is simply a symbolic name. Example MYLIB, KCELLS, etc. sim_model_dir The full path of the directory containing the simulation models of the target library gates. For example, for the cmosis technology, the path is are /CMC/kits/ cmosis5/synopsys/cmosis5.1.1/verilog/nwb and /CMC/kits/cmosis5/synopsys/cmosis5.1.1/verilog/ udp. unit_time The unit of time to be used in the simulation e.g 1ns. resolution_time The simulation resolution, to the unit time. For example, if the unit_time is 1ns, and a resolution of 0.01ns is required, specify resolution_time as 10ps.

In the test bench, include the following lines:

dene HCELLS dir=/CMC/kits/cmosis5/synopsys/cmosis5.1.1/verilog/nwb dene HCELLUDP dir=/CMC/kits/cmosis5/synopsys/cmosis5.1.1/verilog/udp uselib HCELLS HCELLUDP timescale 1ns/10ps

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5.2 Run Simulation and View Waveforms


Run the simulation on the test bench and the HDL le containing the gate-level netlist (the later is the le created in Step 4.26). If you did not do scan test insertion, your gate-level design should have excatly the same port list as your original HDL (behavioral) design and hence no further changes are required to your test bench. Otherwise, if you inserted scan test circuitry, your gate-level design should have two new ports: test_se, and test_si. Therefore, include these ports in the port mapping of the instance of your design in the test bench. Also, include the following statements in the test bench to create reg variables to which these three ports are connected, and in one of the initial blocks, set these variables to 0 (i.e. test_se = 0; test_si = 0;) reg test_se, test_si;

Step 3.2/5.X (Run the Simulation)1 Step 3.3 - Step 3.4/5.X (View the Waveforms)2

Errors, Warnings, & Reports Warning: Too few module port connections... - Manually add the scan test ports (test_se, test_si, and test_so) in the port mapping of the instance of your design in the test bench as suggested above. Warning: Implicit wire has no fanin ... - If this warning is on the three scan test ports mentioned above, simply add the two statements (reg test_se, test_si; and wire test_so;) in the test bench. Otherwise, the warning means that some of the module ports are not connected to anything.

1When

running the simulation, your design le (design.v or design.vhd) must now be the gate-level netlist le created in Step 4.26 (design_g.v or design_g.vhd).

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6
Import the Design to Cadence
Import the HDL or EDIF Netlist to Cadence DFII
wire n1; hnd2 u1 (.op(n1), .p1(a), hdrpq u2 (.q(O), .d0(n1), endmodule a b clk d q c

Now that both the functionality and gate-level timing of the design has been veried, the design is imported to Cadence for cell placement and routing. The design can be imported using the gate-level HDL or EDIF netlist. In this manual, the design is imported using Verilog netlist.

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6.1 Start Cadence Tools


The Cadence software contains all the tools that will be used place and route the design. You must start Cadence from your design directory, with the target technology specied on the command line. After Cadence is successfully launched, the Command Interface Window (CIW) should appear (It takes a few minutes for the software to load!).

To start the Cadence, at the Unix prompt, type: startCds -t technology where, cmosis5 technology The name of the target technology. This must be the same technology that was used to synthesize the design in Synopsys (Step 2.1). Valid technology names (supported by CMC) are: cmosis5 - 0.5 m CMOS. cmosp35 - 0.35 m CMOS. bicmos - Nortel 0.8 m BiCMOS. mitel15 - Mitel 1.5 m CMOS.

TUTORIAL STEP

At the Unix prompt, type:

startCds -t cmosis5

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6.2 Create a Cadence Design Library


The design that you import to Cadence will have to be placed in one of your libraries. If you already have a library earmarked for this, then you should skip this step. Otherwise you must create a new library now.

C icfb - Log:... (CIW) File Tools Options Technology File CMC Gateway CMOSIS5 Help Conversion Tool Box... Library Manager... C Library Manager: Library Path Editor... File Edit View Design Manager Help CheckPlus... New Categories Library... Show Verilog-XL Integration... Open... Cell View... VHDL Tool Box... View Cell Library Open (Read Only) Category... Synergy Tool Box... abstract padvddrcc Open Shell Window basic Synopsys Integration... extracted cdsDefTech padvddring Exit Tantools... layout padvsscore cmcpads Display Resources schematic padvssrcc cmosis5 Mixed signal EnvironLibrary verilog padvssring designFlow Switched Capacitor Name: Automatic Cell CharaMessages DANTES Directory P&I Library Tools .. CDF 1. Type dir1 design_lib Design Flows dir2 Camera dir3 SKILL Development... Design Manager 2. Click Use OK 3. Turn ON OK 4. Click Cancel Help No DM Apply Cancel Help

Errors, Warnings, & Reports

Technology File for library design_lib If you will be creating mask layout or other physical data in this library, you will need a technology le. If you plan to use only schematic or HDL data, a technology le is not required. You can: 6. Click Compile a new techle Attach to an existing techle Dont need a techle

5. Select tech_lib

OK Cancel Defaults Apply Help design_lib cmosis5

New Design Library Attach To Technology Library

DESIGNS design_lib Name of your design library. cmosis5 tech_lib The technology library, e.g. cmosis5, cmosp35, bicmos, mitel15.

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6.3 Import the Verilog File


Import the design Verilog le into Cadence. The reference libraries in the Verilog In form are shadow libraries used to tell Cadence which cells in the Verilog netlist exist in the target technology libraries (hcells and cmcpads libraries for cmosis5). Shadow libraries are required since Synopsys netlists do not contain all required power ports.

C icfb - Log:... (CIW) File Tools Options New Open... Import Export Refresh... Make Read Only... Whats New... Exit... Technology File CMC Gateway CMOSIS5 Help

Errors, Warnings, & Reports

1. Type design_lib

2. Type shadow_libs

EDIF... Verilog... VHDL... CALMP... Help SDL... OK Cancel Defaults Apply Load Save CDL... File Filter Name DEF... LEF... ../ dir1 TEGAS... dir2 SILOS... dir3 Stream... Browse CIF... Target Library Name Applicon... Reference Libraries Verilog Files To Import -f Options Add Add Add Add

10.Click

!
OK

Verilog import completed. Please look at logle ./verilogIn.log Cancel Help

9. Click

OK Cancel Defaults Apply Sheet Symbol Maximum Number Of Rows none 1024

Help

8. Click

Maximum Number Of Columns 1024 Font Hieght Line To Line Spacing Line To Component Spacing Component Density 0.0625 0.2 0.5
Lowest Highest

3. Type design_le

-v Options -y Options Library Extension

4. Type nwb_dir

Ignore Modules File Import Structural Modules As Structural Vie Names Schematic schematic Netlist Symbol netlist symbol schematic

Add Pin Placement Left and Right Sides Import As Functional Pin Placement FileName 7. Type VSS! Full Place and Route Generate Square Schematics Minimize Crossovers Optimize Wire Label Locations Extract Schematics Global Nets Power Net Name Global Signals

All Sides

5. Click

Fuctional functional Log File ./verilogIn.log

Work Area /tmp ./verilogIn.map.table

Name Map Table Overwrite Existing Views Verilog Cell Modules

Create Symbol Only Import As Functional

Import

6. Type VDD!

Ground Net Name

Schematic Generation Options >>

DESIGNS design_lib Name of the design library to import the design into (or the one you created in Step 6.2). _hcells _cmcpads shadow_libs Shadow libraries (described at the beginning of this step). test_g.v design_le The Verilog le to import. This is the gate-level netlist le you saved in Synopsys in Step 4.26. /CMC/tools/cadence/tools/dfII/local/lib/cmosis5/models/verilog/nwb nwb_dir The Cadence directory that contains the Verilog models of the cells in the technology libraries.

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6.4 Open the Schematic


If your design was imported successfully, you should have a schematic view of i in your design library. Open the schematic now.

C icfb - Log:... (CIW)

Errors, Warnings, & Reports

File Tools Options Technology File CMC Gateway CMOSIS5 Help New Open... Import Export Refresh... Help OK Cancel Defaults Make Read Only... Whats New... Cell Names Library Name design_lib 1. Select Exit... design_lib cell1 Cell Name cell_name cell2 cell3 schematic View Name cell4 2. Select Browse cell_name read edit Mode Library Path File your_design_directory/cds.lib 3. Select schematic

4. Click

DESIGNS design_lib Name of your design library. test_chip cell_name The name of your design. This is the name you gave to the top-level module (Verilog) or entity (VHDL). Note that this is NOT the name of the imported Verilog le (even though these two might sometimes be the same).

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6.5 Suppress Solder On CrossOver Warnings


The schematic generated in Step 6.3 might have solders where wires (nets) cross. This will cause warnings when you check the design. Rather than modify the schematic, it is better to just disable these unimportant warnings.

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Current Cellview Hierarchy... Options... Rules Setup... Label Attachment... Find Marker... 1. Turn ON Delete Marker Delete All Markers... Schematic Monitors 2. Click OK Cancel Defaults Apply Packaged Checks Logical Checks None Name Checks ignored ignored ignored ignored ignored ignored ignored warning warning warning warning warning warning warning error error error error error error error

Errors, Warnings, & Reports

Help

Floating Nets Floating Input Pins Floating Output Pins Floating I/O Pins Floating Switch Pins Shorted Output Pins Offsheet Connector Check Physical Checks Unconnected Wires Solder On CrossOver Overlapping Instances Percent Overlap Allowed Maximum Label Offset Max Distance from Wire

ignored ignored ignored ignored

warning warning warning warning

error error error error

Instance/Net Name CollisPin/Net Name Collision Verilog HDL Syntax VHDL Syntax AHDL Syntax Instance Name Syntax Instance Name Expression Pin Name Syntax Pin Name Expression Net Name Syntax Net Name Expression

ignored ignored ignored ignored ignored ignored ignored ignored

warning warning warning warning warning warning warning warning

error error error error error error error error

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6.6 Replace Shadow Library Cells


As mentioned in Step 6.3, the schematic is currently composed of cells from the shadow libraries (i.e. _hcells and _cmcpads for cmosis5). You must now replace these cells with cells from the functional Cadence libraries (i.e. hcells and cmcpads for cmosis5).

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Schematic Layout/Extract Check Supply IO Check and Save Design Hierarchy P&R RET

Errors, Warnings, & Reports Warning: Unable to enter/create cellview... - Ignore these warnings

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6.7 Add Power Pads


Add power and ground bonding pads to the schematic. These will be used to connect power and to the chip. NOTE: This step is to be done twice, rst to add power pads (select padvddrcc in Step 3), and then to add ground pads (select padvssrcc in Step 3).

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Component... Wire (narrow) Wire (wide) Wire Name... Pin... 1. Click Help Hide Cancel Defaults Block... Solder Dot Library Name Browse Cell Names Note View Name Instance Names Array Rotate Columns Upsidedown Rows Sideways 2. Select cmcpads C Library Manager: File Edit View Design Manager Show Categories Library basic cdsDefTech cmcpads cmosis5 designFlow Messages 5. Click1 Cell padvddrcc padvddring padvsscore padvssrcc padvssring View abstract extracted layout schematic symbol 4. Select symbol Help 3. Select padvddrcc

Errors, Warnings, & Reports

Repeat steps 3-5, but select padvssrcc in step 3.

1To

place the selected component in the schematic, simply left-click anywhere in the schematic editor window. But make sure that the component does not touch other parts of the circuit.

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6.8 Check Supply I/O


Use a CMC-provided script to verify that appropriate power/ground pads are included in the schematic. Make sure that you get the IO check OK report in the CIW.

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Schematic Layout/Extract Check Supply IO Check and Save Design Hierarchy P&R RET

Errors, Warnings, & Reports Warning: Failed to open cellview... - Ignore these warnings Report: IO check OK. - If you dont get this report in the CIW, then there is something you have done wrongly. You should correct the mistake you made, or simply redo all the steps from Step 6.3.

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6.9 Check and Save the Design Hierarchy


Finally, check that the whole schematic is OK. Checking will also save the schematic if there are no errors. Again, if terrors or warnings that you dont understand are reported, you should not proceed. Some warnings (mentioned below) are normal and can be ignored.

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Current Cellview Hierarchy... Options... Rules Setup... Label Attachment... Find Marker... Delete Marker Delete All Markers... 1. Click Schematic Monitors

Errors, Warnings, & Reports Warning: Pin WORLD on ... oating ... - Ignore these warnings

OK

Cancel

Defaults

Apply

Help

Process Referenced Libraries Save Schematics View Name List

only those that need it every schematic check do not check yes SpectreS no those with errors Ask Me extracted schematic symbol

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7
Place and Route the Design
Place and Rout the Design Using Cell Ensemble
a b clk d q c

In this step, you will layout the chip. First, the pads and gates are placed, and then the design is routed.

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7.1 Open the Design in a Hierarchy Browser


From the schematic editor, open the design in a hierarchy browser, from where you will be able to create an autoLayout view. NOTE that to launch the hierachy browser, the schematic editor menus must rst be changed to Floorplan/ Schematics menus.

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Mxd-Sig CMC Skill Help Analog Artist Datapath/Schematic Design Synthesis Diva Floorplan/Schematics Mixed Signal Opts. Module Maker Schematics Simulation

Errors, Warnings, & Reports

C Composer - Schematic Editing: ... Tools Design Window Edit Add Check Sheet Floorplan CMC Skill He Hierarchy Browser... Cross Select Cross Highlight 1. Click

OK

Cancel

Defaults

Apply

Help

Library Name DESIGN Cell Name View Name test_chip schematic

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7.2 Specify the Chip Global Signal Names


Specify the names for global signals, i.e. global power signal name and global ground signal name.

C Hierarchy Browser: ... Window Utilities Hierarchy Help Deselect All Cross Select Cross Highlight Environment...

Errors, Warnings, & Reports

OK

Cancel

Defaults

Apply

Help

======Display Options====== Instance Node Label Instance Filter Instance Count On Node Tree Expansion Direction Tree Routes Fit Tree Graphics in Window ======Expand Options====== Levels

instance name master name IO block core cell vertical levered horizontal fan

1 all

======Generate AutoLayout/AutoAbstract Options====== Default Area Estimation Function Default Area Utilization (%) Default Area Per Gate simple 80 10 1. Click

Change Default Global Signal Names Obstruction On Block Hierarchy Delimiter Character

OK

Cancel

Defaults

Apply

Help 2. Type tech_lib

Library To Store New Global Names Global Power Signal Name Global Ground Signal Name Use Existing Global Names vdd! gnd! in Library

3. Click

cmosis5 tech_lib The technology library, e.g. cmosis5, cmosp35, bicmos, mitel15.

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7.3 Generate an AutoLayout View


Create the autoLayout view.

C Hierarchy Browser: ... Window Utilities Hierarchy Expand Selected Unexpand Selected Generate Physical Hierarchy Generate Abstract From Symbol Properties Help

Errors, Warnings, & Reports Report: The layout hierarchy has been created successfully. - If you dont get this report in the CIW, then there is something you have done wrongly. You should correct the mistake you made, or simply redo all the steps.

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7.4 Open the AutoLayout


Open the autoLayout into the Virtuoso layout editor. You do this from the Command Interpreter Window (CIW). ASfter a few seconds, the layout editor (shown in Step 7.5) should appear.

C icfb - Log:... (CIW)

Errors, Warnings, & Reports

File Tools Options Technology File CMC Gateway CMOSIS5 Help New Open... Import Export Refresh... Help OK Cancel Defaults Make Read Only... Whats New... Cell Names Library Name design_lib 1. Select Exit... design_lib cell1 Cell Name cell_name cell2 cell3 schematic View Name cell4 2. Select Browse cell_name read edit Mode Library Path File your_design_directory/cds.lib 3. Select autoLayout

4. Click

DESIGNS design_lib Name of your design library. test_chip cell_name The name of your design.

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7.5 Start Cell Ensemble


Cell Ensemble is the place and route engine that will be used to automatically place and route the design. You start Cell Ensemble from the layout editor menus. Again, notice that the Cell Ensemble menus (shown in Step 7.6) are slightly different from the layout menus shown in this step.

C Virtuoso Editing: ... Tools Design Window Create Edit Verify Misc CMC Skill Abstract Analog Artist Compactor Device-Level Editor Device-Level Router Floorplan/P&R Base Array Editor InQuery Block Ensemble Layout Cell Ensemble Layout Synthesis Cell3 Ensemble Microwave Datapath/Cell Ensemble Module Maker Datapath/Cell3 Ensemble Pcell Gate Ensemble Simulation Structure-Compiler Verilog-XL Help

Errors, Warnings, & Reports

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7.6 Initialize the Layout


Initialize the layout. This will place all the pads and gates outside th placement area. Because for small layouts the core cells will have a small area relative to the area occupied by the pads, the aspect ratio is adjusted to reduce this amount of white space around the core cells. Also, an aspect ratio of less than 1.0 results in a vertical core which Cadence can route more efciently than a at core. This is more signicant for small designs.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Reinitialize... I/O Place... Partition Block Place... Soft Pins Update AutoLayouts... Floorplan File Synthesis Link Replace View... Help

Errors, Warnings, & Reports

OK

Cancel

Defaults

Apply all regions chip size special routing IOs macros lower left

Help none groups instances status nal routing standard cells

Initialize

Preserve pre-placed Chip Origin Estimate Design Size Chip Aspect Ratio (Width/Height) Load a Floorplan File Load a SDF File

File Name File Name

1. Type 0.8

2. Click

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7.7 Place the Design


In this step, you will place the pads and the standard cells automatically.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC IO Commands Automatic... Qplace... CTS Place... Spare Cell... Power Cell Glue Cell Snap To Grid... Sequencer... 1. Click Check... Help

Errors, Warnings, & Reports

OK Cancel Defaults Apply Method Insert Feedthru Feedthru Library Name hcells Feedthru Master Name hft Feedthru Master View Placement Snap Grid Mirror Cells Browse Options Initial Improve abstract 0.1 initial improve

Help both

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7.8 Insert I/O Corner Cells


Insert I/O corner cells. If you have not already done so, you should rst copy the le glue.map from the technology samples directory (this is usually /CMC/kits/technology/cadence/technology.version/samples) into your design directory. For the tutorial, make sure you are in your design directory and at the Unix prompt, execute the following command: cp /CMC/kits/cmosis5/cadence/cmosis5.2.3/samples/glue.map .

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Read Initial File... Justify... Add Corners... Place Route CMC IO Commands Automatic... Qplace... CTS Place... Spare Cell... Power Cell Glue Cell Snap To Grid... Sequencer... Check... Help

Errors, Warnings, & Reports

OK Cancel Defaults Apply Glue Cell Library Name cmcpads Glue Cell Master Name Glue Cell Master View abstract Browse Net Association match TermName none

Help

1. Type CORNERc

2. Type ./glue.map le

Terminal Mapping File

3. Click

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7.9 Create Routing Channels


Create the channels that will be used for routing the chip.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Display Cutlines... Channels Remove Cutlines... Modify Net Create... Special Net Route Delete Global Route Detail Route Sequencer... 1. Click Check... Help

Errors, Warnings, & Reports

OK Cancel Defaults Apply Initial Cut Channel Name Cut With Barriers vertical Channels horizontal

Help automatic

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7.10 Set Net Properties


Set the net properties from a le. There is a sample le in the Cadence directory, which should have been copied into your working directory. Make sure that this le is in the current directory, otherwise specify the full path to it in the File Name eld below. The sample le, called net.props, is in the same directory as the one used in Step 7.8.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Channels Modify Net Properties... Modify Net Special Net Route Net Properties File... Global Route Split Net Detail Route Unsplit Net Sequencer... Check... Help

Errors, Warnings, & Reports

1. Turn ON OK Cancel Defaults Apply Net Properties File Nets Properties File Name Properties To Save write all P&R Help read selected 2. Turn ON all 3. Type ./net.props

4. Click

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7.11 Route the Global Signals


Global signals include power and ground signlas. These signals have to be routed rst.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Channels Modify Net Special Net Route Global Route Automatic... Detail Route Delete... Single Net Global Route... Sequencer... Interactive Global Route... Check... Display Channel Density... Remove Channel Density... Adjust Channel Density... Topology Display... Global Routing File... 1. Click Help

Errors, Warnings, & Reports Error: ..auiGetBoolFieldValue error.. - Ignore this error.

OK Cancel Defaults Apply Method Options both Automatic auto

Help optimize

Optimizer

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7.12 Route the Whole Chip


Now route all the other signals.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Channels Modify Net Special Net Route Global Route Detail Route Switch Layer... Sequencer... Reserve Tracks... Check... Automatic... Delete... Explode Channels 1. Click Strip Outer Channels... Help

Errors, Warnings, & Reports Error: ..auiGetBoolFieldValue error.. - Ignore this error.

OK Cancel Defaults Apply Compaction Mode Contact Style Add Conditional Via Tie Pin To Cell Instance Routing Layers automatic centered rigid offcentered

Help rigidIO pushed

2 or 2 1/2 Layers

3 Layers

Max Vert Jog Length for half-layer Max Horiz Jog Length for half-layer Options Compact

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7.13 Run the CMC Scripts


Run the two CMC scripts. The rst one ..., and the second one prevents bad shape errors on the VIA12 and VIA23 instances when a DIVA DRC is performed..

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Help Schematic Layout/Extract Slot wide metal3 busses P&R RET Flatten SymbolicVias

Errors, Warnings, & Reports

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Help Schematic Layout/Extract Slot wide metal3 busses P&R RET Flatten SymbolicVias

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7.14 Create a Layout View


To create a layout view of the design, replace the views of all the design cells with their layout views. NOTE: normally after completing this step, the design cells will be displayed with instance views. To display the attened views, press shift-f. To go back to instance views, press control-f.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Reinitialize... I/O Place... Partition Block Place... Soft Pins Update AutoLayouts... Floorplan File Synthesis Link Replace View... Help

Errors, Warnings, & Reports

OK

Cancel

Defaults

Apply selected layout

Help all

Instances To Work On To View Name

3. Click

2. Select layout

1. Turn ON

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7.15 Save the Design


You must save both the autolayout and layout views of the design. If you want to re-run the aouto place and route again, you do it on the autolayout view. Otherwise the remaining steps, Design Rule Checking (DRC) and Layout Versus Schematic (LVS) will be done on the layout view. After this step, you may close the autoLayout editor window.

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Save Save As... Discard Edits Load... Make Read Only Show Selected... Hierarchy Plot Options Environment Help

Errors, Warnings, & Reports

C Virtuoso Editing: ... Tools Design Window Create Edit Floorplan Analyze Place Route CMC Help Save Save As... Discard Edits Load... 1. Type Make Read Only 2. Click layout Show Selected... Hierarchy Plot Help Apply OK Cancel Defaults Options Environment Library Name DESIGN Cell Name View Name test layout

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7.16 Place the CMC Logo


All designs submitted to CMC for fabrication should have a logo that is typically a 5-character string composed of your Universitys two-character ID followed by three characters chosed by the designer. In this tutorial, we will create a logo with CMCs ID IC followed by the string XXX. The logo is added to the layout view. So make sure you close the autolayout view in Step 7.15. Take note that this step is performed in two windows: the layout window and the CIW window.

Open the Layout View (Step 7.4)1


C Virtuoso Editing: ... Tools Design Window Create Edit Verify Misc CMC Skill Abstract Analog Artist Compactor Device-Level Editor Device-Level Router Floorplan/P&R InQuery Layout Layout Synthesis Microwave Module Maker Pcell Simulation Structure-Compiler Verilog-XL Help

Errors, Warnings, & Reports

C icfb - Log:... (CIW) File Tools Options Technology File CMC Gateway CMOSIS5 Help CMC-Added Documentation On Connecting to CMC On Getting Help with Cadence Tools Bug Submission Form Start Cadence Documentation Place Logo

1When

opening the layout view, make sure you select layout on the View Name.

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From RTL Description to Layout

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