Amir Saka 060136322 Oded Friedmann 043144799

Micro Architecture Lab Execise 1

Part A 1. ok 2. This is a tool that simulates the behavior of a computing device. We use it for the following reasons: a. It allows us to test and examine device's ability in the design stage, before actual implementation on HW. b. Different designs can be tested before actual implementation on HW, and allow us to choose the best design c. Gives us the option to test larger variety of scenarios and configurations until we get an optimal result d. level of abstraction can be throttled to design task 3. Types of architectural simulators: a. Functional simulators There are trace driven simulators Vs. Exec driven simulators. b. Performance simulators Instructions schedulers Vs. Cycle Timers. Simple scalar simulator is Exec driven and Cycle Timer. 4. The simple scalar tool set includes compilers, assembler, linker and simulators. It also has the ability to get Assembly code directly. 5. The Simpler scalar simulation suite includes: Type Sim-Fast Sim-Safe Sim-Profile SimCache/Cheetah Sim-Outorder Functional/Performance Functional Functional Functional Functional Performance No of lines 420 350 900 1000> 3900 Other MIPS +4 W/ checks Lots of stats Cache stats OoO issue branch pred, mis spec, ALU, cache, TLB, 200+ KIPS

6. SPEC2000 benchmark suite: A set of benchmarks for standard CPU (and memory) performance measuring and evaluation. There are two main parts: CINT2000 set of Integer programs. CFP2000 set of Floating-point programs. 7. ok 8. ok attached file: q8.txt 9. attached files are: cache32.simout, cache64.simout We changed the size of the cache and ran it once with 32kb and once with 64kb. Miss rate in the first time (32kb) was: 0.0903 Miss rate in the second run (64kb) was: 0.0335

10. the command we used was: cut cache.simout |grep I sim_num_insn > parsing_example.txt Part B 11. Out-Of-Order (OOO) speculative execution is a term that refers to a CPU that executes instructions, not necessarily in their order of appearance bu commits them in order. This is possible by performing the actual calculations without writing the results to the memory. Speculative Execution when branch instruction is executed, the CPU is allowed to predict if the branch will be taken or not taken (there are different methods for predications) and continue execution according to the prediction. If it turns out to be wrong, it is able to restore the status before the prediction. 12. Sim-Outorder Simulator: Performance simulator, which implements OoO processor, including two memory levels and speculative execution. Simulator options (3 chosen): - -issue:inorder determine if processor issues instructions inorder. - -max:inst maximum instructions to execute. - -ptrace <file_name> x:y enable pipeline trace of execution range. 13. Architecture pipeline: Fetch Deco Exe Mem WB

Fetch reads instruction from memory, stores it in PC and advance PC by 4. Includes ALU, register and MUX. Decode reads data from registers, determines instruction type. Includes Registers and sign extension unit. Execute execute ALU commands or memory address calculation. Includes 2 MUX and ALU. MEM reads/writes from/to memory. WB writes ALU result to result register.

14. The output of the command was many blocks such as the following one: First is the cycle number: @ 3974 Then a list of the instructions that were fetched: dn = `0x120028af0: [internal ld/st]' do = `0x120028af4: [internal ld/st]' dp = `0x120028af8: [internal ld/st]' dq = `0x120028b00: stq r17,56(r16)' dr = `0x120028b04: stq r17,40(r16)' ds = `0x120028b08: stq r17,48(r16)' And then the state of the pipeline: [IF] [DA] [EX] [WB] [CT] dm cz dd ct cr* dq dc cx cs* dr df cy cv* ds dg da cw* dh db di de dj dk dl dn do dp Attached are the output.trc and q14.txt files. 15. We ran the following commands: Without config: /local/arch_lab/Simple_Scalar/simplesim-3.0/sim-outorder -max:inst 8000000 /local/arch_lab/spec2000binaries/ sixtrack.peak.ev6 With config: /local/arch_lab/Simple_Scalar/simplesim-3.0/sim-outorder -config /local/arch_lab/Simple_Scalar/simplesim-3.0/config/outorder_2.cfg /local/arch_lab/spec2000binaries/ sixtrack.peak.ev6 There was a problem with the config file that generated an error in the run. The IPC on the first run was: 1.7666 Files attached: q15_no_config.txt , q15_config.txt 16. Again we ran without config file. In the second run we added the -issue:inorder tag. The IPC in the outorder run was: 1.7666 The IPC in the inorder run was: 0.8856 As we expect, executing commands out of order is much better than in order execution. Attached are the files: q16_inorder.txt, q16_outorder.txt

17. Parameter

We changed the script to run bzip2 & eon and got the following results: bzip2 25000002 25939609 2.6890 0.7385 0.0000 0.9975 9975 0.0000 0.0008 0.3793 eon 25000003 33144231 1.9206 0.1061 0.0000 0.9371 0.9714 0.0000 0.0005 0.1551

sim_num_insn sim_total_insn sim_IPC ruu_full lsq_full bpred_comb.bpred_addr_rate bpred_comb.bpred_dir_rate il1.miss_rate dl1.miss_rate ul2.miss_rate

18. FP: mesa 3 dimension graphic program in C, which converts 2-D scalar field data to 2-D PNG (Portable Networks Graphics) image. INT: twolf C program that finds parameters needed for microchip design. Uses heuristic methods to find the best solution according to specific design rules. Outputs the location and layout of all pins. vpr C program for integrated circuit design. The program get as an input file describing the netlist and outputs files containing the best FPGA design it could find + statistics and validity checks results of this design.