Performance Limits of Silicon MOSFETs

Farzin Assad, Zhibin Ren, Supriyo Datta, and Mark Lundstrom

Purdue University, West Lafayette, IN USA 47907-1285

Peter Bendix
LSI Logic Corporation, Milpitas, CA 95035 this degenerate Fermi gas depends on the sub-band occupancies and is readily calculated [2]. The maximum velocity at the source approaches the thermal injection velocity when few of the thermal carriers injected into the channel back-scatter to the beginning of the channel [3]. The on-current of a nanoscale MOSFET displays a strong sensitivity to the low-field mobility because it determines the back-scattering in the critical region at the beginning of the channel [3]. Real devices operate below the ballistic limit because of carrier back-scattering, which leads to

Abstract A procedure for comparing the current vs. voltage characteristics of MOSFETs against their upper limits is described, and a 0.35 m n-MOS technology is assessed. Channel back-scattering coefficients for this technology are deduced where we show that the on-current performance is ~45% of its upper limit. We also show that conventional device scaling maintains approximately the same level of device performance, and we discuss the implications for the ITRS on-current performance targets. Finally, we compare the upper limit performance of a p-channel vs. an n-channel MOSFET technology. Introduction CMOS technology has evolved to a stage where device performance should be assessed against upper limits. The purpose of this work is to do so. We compare the measured performance of a 0.35m technology against its upper limit characteristics [1,2] and show that the measured on-current is ~45% of the upper limit. We show that the channel resistance has a lower limit, no matter how short the channel is or how high its mobility and that the magnitude of this fundamental channel resistance is large enough to influence practical devices. Real devices operate below their fundamental limit because of channel back-scattering [3]. We present a procedure for extracting the channel back-scattering coefficient, r, as a function of gate and drain bias. We show that the values extracted from measurements are consistent with simple estimates and discuss the differences between nand p-channel MOSFETs. We show that a simple, oneparameter scattering model accurately predicts the characteristics of a well-tempered MOSFET all the way to their limits. We also show that conventional MOSFET scaling practices maintain a constant r and that the NTRS oncurrent targets near the end of the roadmap are not achievable by conventional device scaling. Scattering Theory of the MOSFET Carrier transport in nanoscale transistors involves socalled off-equilibrium transport, but the essential features are easy to understand. The beginning of the channel is a quasiequilibrium point populated by thermal equilibrium electrons injected from the source. The positively-directed velocity of

I DS / W = CoxT
and [3]

(1 r ) (V V )V GS T DS 2k B T / q

(2a)

1 r I DS / W = CoxT (VGS VT ) 1+ r
valid when

(2b)

V DS << k B T / q for equation (2a), and VDS >> k BT / q for equations (2b). The critical parameters are the source injection velocity, T, and the channel backscattering coefficient, r (0 < r < 1).
Results The channel injection velocity, T , is a critical parameter in the theory. It is important because it is the maximum velocity achievable at the source end of the channel and consequently it limits the maximum current that can be delivered. It is gate-bias dependent because it depends on how the sub-bands are occupied and on the carrier degeneracy. Figure 1 compares T obtained for 250 nm and 50 nm generation n-channel technologies. For each technology, two kinds of channel profile are shown: (i) uniform channel doping (solid) and (ii) retrograde channel doping (open circles). Also shown is the injection velocity for the holes for a uniformly doped 50nm generation pchannel technology. The results were obtained using a selfconsistent SchrdingerPoisson solver [2], where we used a simple valence band model which neglects the band structure warping for the holes [8]. Modeling holes, because of their

complicated constant energy surfaces and light and heavy band degeneracy is, in general, difficult but Takagi et. al. [8] showed that a simple, two-band, ellipsoidal model produced good agreement between their theoretical results and CV data obtained from p-MOSFETs. We use their simple model to estimate T for the holes. Figure 1 shows that T for the 50 nm device is higher than the 250 nm device, but there is virtually no difference between the uniform and retrograde channel doping. The injection velocity depends on the total inversion layer density, ns , but also on how the inversion layer is distributed among the different sub-bands. A higher substrate doping tends to increase the well confinement causing the higher lying energy levels, with their heavier masses, to be populated more sparsely. For the 50nm device the substrate doping is higher, therefore the carriers would exclude occupying the higher sub-bands and would instead occupy the first sub-band which has a lighter effective-mass and hence higher injection velocity. For the L poly = 0.30 m n-MOSFET examined next, T ~ 1.4 x 10 cm/s at a VGS =3.0 (V).
7

Equation (2) shows that to maximize the on-current, we need to minimize the channel back-scattering coefficient, r. In Figure 3 we show r extracted for the 0.3 m device as a function of gate voltage, where equations (2a) and (2b) were used to extract r for the V DS low (linear regime) and V DS high (saturation regime) biases. The back-scattering coefficient is determined by the electric field near the source [3]. Under low V DS , the field is low and r ~0.9; for high

V DS the field increase and r ~0.4.

2000

1500

(A/m) I
DS

1000

500

0
2.2 107 2 107

0.5

1.5

2.5

DS

(V)

Injection velocity (cm/sec)

1.8 10

1.6 107 1.4 10

7

50 nm generation

Fig. 2 The measured IDS vs. VDS characteristic of an Lpoly = 0.30 m nMOSFET at VGS = 3.0V (solid line). Also shown is the upper-limit characteristic for this device with (dotted line) and without (dashed line) the measured series resistance included.

1.2 107 1 107 8 106 6 106 1010

250 nm generation
1

hole velocity
0.8
1011 1012 1013 -2

N (cm )
s

0.6

Fig. 1 The computed channel injection velocity vs. inversion layer density. Two kinds of channel profiles are examined: a uniform channel profile (solid lines) and a retrograde profile (circles), shown for 250 nm and 50 nm generation technologies. Results for a uniform profile p-channel 50nm technology are also shown.

r
0.4 0.2

In order to assess the performance of a 0.35 micron technology, we show the measured I DS VDS characteristics for a L poly =0.3 m device, taken at VGS =3.0 (V), in Figure 2. The technology used to make this device utilizes a physical oxide thickness t ox =6.5 nm and is designed to have a VT ~0.6 (V) for a 0.35 m device. Also shown in Figure 2, is the calculated ballistic current for an ideal device (long dashes) excluding parasitic resistance and the ballistic current for a non-ideal device (short dashes) including the measured parasitic resistance for the device. As expected, the parasitic resistance causes the ballistic current to saturate at a higher drain voltage, but more importantly, it significantly degrades the ballistic on-current, reducing it by ~30%.

0 1.5

2.5

GS

(V)

Fig. 3. The extracted channel back-scattering coefficient for the 0.30 micron n-MOSFET vs. gate voltage for low VDS (dashed line) and for high VDS (solid line).

Finally, in Figure 4 we show the channel resistance (solid line), defined as the total measured resistance minus the parasitic resistance, plotted as a function of gate voltage. Alongside the channel resistance, we show the ballistic resistance (dashed line) as evaluated from equation (2a), but generalized to include multiple sub-bands and carrier degeneracy [2]. The ballistic resistance is not expected to be important unless Leff becomes comparable to a mean free

path, however, for the 0.35 m technology studied here it is already a measurable fraction of the total resistance.
2000

the characteristic distance to proportionately decrease causing r to be fixed to ~0.4. According to equation (2b), the measured on-current 1 r . For this is a fraction B of the ballistic limit where B= 1+ r device r~0.4, which yields a B of 0.45. It is somewhat surprising that such a long channel device (~15 MFPs) operates so close to its upper limit but the reason can be explained by using equation (3): once the carriers injected into the channel pass beyond the length , they will never back-reflect and hence it is the length that determines the on-current and not the entire channel length. To extract a larger on-current, then, we would need to minimize the ratio / but at the same time we need to maintain the off-current correspondingly low. Conventional scaling strives to maintain the same on-current while maintaining a low off-current. Our analysis of the 0.35 m technology shows that this technology is characterized by a channel back-scattering of ~0.4 but our analysis of other devices [6] indicates that for more aggressively scaled technologies, the back-scattering coefficient continues to be close to 0.4 independent of technology generation. In Figure 5 we show the simulated I DS V DS characteristics of a hypothetical 25 nm device, obtained using a Monte Carlo program [7] and compare it with the current calculated using the scattering theory, equation (2b). The good agreement shown indicates that conventionally scaled devices will continue to be characterized by r ~0.4.
1200

Resistance ( m)

1500

1000

500

0 1.5

2.5

GS

(V)

Fig. 4 The measured channel resistance vs. gate voltage for the 0.30 micron n-MOSFET with series resistance effects removed (solid line). Also shown is the fundamental channel resistance (dashed line)

Discussion According to scattering theory, the ratio of the two resistances plotted in Figure 4 is given by / L poly , where is the mean free path (MFP). Assuming a L poly of 0.3 m, the ratio provides an estimate of ~18 nm which is consistent with ~21 nm, deduced from the measured mobility data obtained at VGS =3.0 (V), but this agreement should be regarded with caution. The device examined here is much longer (~15 times) than the expected MFP, which makes the estimate susceptible to measurement errors. For the nano-scale MOSFET, however, we expect the fundamental resistance to be a more readily measurable quantity. We have shown that for the 0.3 m device, the channel back-scattering for VD = VDD is ~ 0.4 independent of the gate bias, but we can readily explain this using scattering theory. When the drain bias is high, the energy bands have large gradients near the drain end and therefore the non-local effects will be important. But for a welldesigned MOSFET the energy bands near the source end, despite the large field gradients near the drain, will only bend gently and, indeed, we can show that transport is controlled by a small region near the source end. To be specific, we can show that r is given by:

1000

(A/m) I
DS

800

600

400 200

0 0 0.2 0.4 0.6 0.8 1 1.2

DS

(V)

r=

1 = + 1+ /

Fig. 5 Comparison of the scattering model (solid line) with IDS vs. VDS characteristics of the n-MOSFET reported in [7] as obtained by Monte Carlo at VGS=1.1 (V).

(3)

where is the distance it takes for the electrons to drift ~ k BT / q down the channel from the top of the source barrier.

As the gate voltage increases, decreases but the electric field near the source barrier will also increase. This causes

Looking ahead towards the end of the roadmap, it is not at all clear whether or not the on-current targets in the NTRS may be met. In Figure 6 we show the projected oncurrent performance at various nodes of the NTRS-97, where we have obtained the device parameters t ox , N sub , and

VDD straight from the NTRS-97, but for the threshold

N (/cm )

voltage, we assumed VT = V DD / 5.0 . Since the threshold voltage may not be scaled below a minimum value, which is set by the off-current requirement (~0.2 V ), we took VT =0.2 (V) for the last two nodes of the NTRS-97. Comparing against the roadmap target of 600 A/m, it is apparent from Figure 6 that the future technologies will have to operate much closer to the upper limit in order to achieve the targets. In Figure 7a, we compare the ballistic current calculated for a p-channel device with that calculated for an n-channel device, at the 50 nm node of the NTRS-97. The difference between the on-currents between an n- and pchannel device is commonly argued to be due to the difference in the saturation velocity between electrons and holes, but Figure 7a suggests that even in the absence of scattering, the p-MOSFET would still under-perform its nchannel counterpart by about a factor of 2!. Figure 7b clarifies the reason behind this: at a given gate voltage, the inversion density for a p-channel device, as pointed out in [8], is somewhat lower because the effective gate capacitance is lower. More importantly, the thermal injection velocity, due to the heavier mass of the holes, is also smaller. These two effects conspire to produce a lower on-current in a ballistic p-MOSFET.

1.2 10

13

2.5 10

1 10 8 10
2

13

2 10
12

(cm/sec)

1.5 10 6 10
12 7

1 10 4 10 2 10
12

12

5 10

0 10

0.2

0.4

0.6

0.8

0 1.2

V (V)
GS

Fig. 7b Inversion density and injection velocity as computed for the nchannel (solid line), and p-channel (dashed line) device at the 50 nm node of the NTRS.

2000

1200

On-Current (A/m)

1500

1000

1000 800

(A/m)

500

600
0

DS

400 200

2000

2002

2004

2006

2008

2010

2012

Year

0 0 0.1 0.2 0.3 0.4 0.5 0.6

Fig 6. Projected ballistic current vs. time for several future technologies as obtained from the NTRS-97. The circles are the calculated on-current with no parasitic resistance and the triangles include a parasitic resistance equal to 10% VDD/Ion. Also shown (dashed line) is the target on-current.

V (V)
DS

Fig. 7a Comparison of the calculated ballistic current for a n-channel and p-channel (solid line) device at the 50 nm node of the NTRS-97.

References [1]
K. Natori, J. Appl. Phys., 76, pp. 4879-4890, 1994. F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. S. Lundstrom, to appear, IEEE Trans. Electron Devices, Jan 2000. M.S. Lundstrom, IEEE Electron Dev. Lett., 18, pp. 361-363, 1997. M.S. Lundstrom, IEDM Tech, Dig., 387-390, 1996. Y. Taur, C.H. Wann, and D.J. Frank, IEDM Tech. Dig., 789-792, 1998. F. Assad, Z. Ren, D. Vasileska, S. Datta, and M.S. Lundstrom, Tech. Proc. MSM 99, pp. 100-102, 1999. Y. Taur, C. H. Wann, and D. J. Frank, IEDM Tech. Dig., pp. 789-792, 1998. S. Takagi, M. Takayanagi, and A. Toriumi, IEEE Trans. Electron Devices, 46, pp. 1446-1450, 1999.

Summary In summary, we present a simple, physical model which shows that there is an easily calculated, upper limit to a MOSFETs on-current and a lower limit to its channel resistance. Present-day MOSFETs operate surprisingly close to these limits, even though channel lengths are still many (> 15) mean-free-paths long. This work identifies device limits and provides a way to assess new device approaches against those limits. Acknowledgment- This work was supported by DARPA under the Advanced Microelectronics Program and the Semiconductor Research Corporation.

[2] [3] [4] [5] [6] [7] [8]