FACULTY OF ELECTRICAL ENGINEERING UNIVERSITI TEKNOLOGI MARA MALAYSIA

ELE 653
LAB 1

Synthesis Lab
TASK 1 PREPARED BY:

AHMAD AL-ZUBIR BIN ZULKIFLY

2009435996

GROUP: EE2108A

LECTURER: Puan Siti Lailatul Mohd Hassan

1.0. Introduction
Synthesis is a complex task consisting of many phases and requires various inputs in order to produce a functionally correct netlist. The following lab presents the basic synthesis flow with Synopsys Design Compiler. It assumes that you have a synthesizable and functionally correct HDL description available. Synthesis with Design Compiler include the following main tasks: reading in the design, setting constraints, optimizing the design, analyzing the results and saving the design database. Design Compiler supports a wide range of flat and hierarchical design styles. Combinational and sequential designs can optimized for timing, area and power.

2.0. Objective To perform logic synthesis operation on a Verilog source code using Synopsys
Design Compiler (DC). To learn verilog code for simple counter. To fimiliar with Graphical User Interface Tool called Design Vision. To perform synthesis using DC shell interface To create a script file containing all the design constraints. To create another command script file to run the synthesis process in batch mode.

3.0.

How Synthesis Work

Figure 1: Process of Synthesis.

4.0. Method
Basic Synthesis Flow

Figure 2 : Basic Synthesis Flow Chart. START Go to directory task1 DC Setup Read & Link Design Design Constraints Optimize Design Save the Design Analyze Design END Figure 3 : Flow Chart of Task
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5.0. Result

a)

DC Setup

Figure 4: A Setup File That Specifies The Standard Cell Library.

b)

Read & Link Design

Figure 5: DC Commands to Verify Library Settings.

Figure 6: Block Diagram of Counter.

Figure 7: Schematic View of The RTL Code.

c)

Design Constraints

Figure 8: DV Command Prompt Using TCL Syntax.

d)

Optimize Design

Figure 9: Schematic RTL was Changed After Optimized.

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e)

Save the Design

Figure 10: DV Command Prompt Use To Save The Design. f) Analyze Design

Figure 11: Report Area of The Design Counter.

Figure 12: Report Clock of The Design Counter.

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Figure 13: Report Clock_Skew of The Design Counter.

Figure 14: Report Timing of The Design Counter.

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TASK 2
DC Setup Firstly we create the constraints file. These are similar constraints to Task 1. Then we check any syntax errors and there are no errors, dcprocheck will return the following message below:

Figure 15: The the constraints file of the Design Counter. Read & Link Design -> Design Constraints -> Optimize Design -> Save Design

Figure 16: Script commands of the Design Counter.

Figure 17: Script commands of the Design Counter.

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a)

Analyze Design

Figure 18: Report Area of Counter

Figure 19: Report Clock and Report of Clock_Skew of Counter.

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Figure 20: Report timing of of The Design Counter.

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6.0. Discussion
We run logic synthesis operation on a Verilog source code using Synopsys Design Compiler (DC). Design Compiler can simulate using three interface. We can use Design Vision (interactive GUI), DC Shell (interactive shell) and Batch mode. This simulation exercise will use Design Compiler graphical user interface tool called Design Vision. The design used is a simple counter. Firstly, we need to go to directory task 1. Then, we launch DC GUI to simulate the verilog code of counter. From Figure 1 showed the Process of Synthesis. It is described as translation + logic optimization + mapping. In terms of the Synopsys tools, translation is performed by the read_vhdl/read_verilog commands. Logic optimization and mapping are performed by the compile command. From Figure 2 showed Basic Synthesis Flow Chart. It have eight of step to do synthesis in any design. At step 3 (Read design), that mean it reads VHDL/Verilog files, performs syntax and synthesis-policy checks, then builds the design using generic (GTECH) components. At step 5 (Set design constraints), that mean it is not a Design Compiler command, but a series of steps you perform to tell Design Compiler what our timing and area requirements are. At step 6 (Optimize the design), that mean it is optimizes a design and maps it to real gates from your target technology library, producing a circuit that meets your constraints. From Figure 4 showed a setup file that specifies the standard cell library. Before we can start using DC Setup, we will need to create a setup file that specifies the standard cell library that we are going to use and its location. Using gedit, create a file called ".synopsys_dc.setup". From Figure 5 showed DC Commands to Verify Library Settings. It is step for Read and Link Design. We launch the DC GUI, Design Vision (DV) and typing the DV command prompt at the bottom of the DV window. So we verify that library settings in the ".synopsys_dc.setup" file was applied correctly. From Figure 6 showed Block Diagram of Counter. This will show the input ports on the left and output ports on the right.

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From Figure 15 showed The the constraints file of the Design Counter. These are similar constraints to task 1 but we save in scripts/constraints.tcl. After we run the command there are no errors, dcprocheck will return the following message like Figure 2. From Figure 16 and Figure 17 showed Script commands of the Design Counter. In this section which will read in the design, apply the constraints, compile the design, generate reports and exit the tool.

From Figure 20 showed Report Timing of The Design Counter. We get the value of slack (MET) same as manual is 1.061.

7.0. Conclusion
For the conclusion, it can be conclude that all the objective has been fulfill. This lab makes student to more competible using a Synopsys software. We learn how to simulation using Synopsys DC using DC's graphical user interface tool called Design Vision. Thus, we also know and learn verilog code for simple counter.

So with study and learn Task 1 and Task 2, we can fimiliar and friendly with Synopsys Eda Tools.

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