Lecture # 01

Basics of Computer System Architecture

Computer Systems

Computer System can be divided into two parts:

Hard ware Soft ware

Hard ware can be defined as All the physical entities which constitute a computer System
Soft ware can be defined as The programs and Data to be operated upon

The hard ware can further be divided into three parts. Central Processing Unit (CPU) I/O Processor Memory

Computer Systems

The CPU contains an ALU portion for manipulation of data and internal registers for storage and control circuits for fetch and execute process.

The Memory contains storage for Instructions and data. It is called as RAM, because any location can be accessed randomly.

The I/O processor contains electronic circuits for transfer of Info: between CPU and i/o devices (Keyboard, Printer etc).

Computer Systems Architecture

Computer Architecture is concerned with the structure and behavior of the computer seen by the user. It includes: Information Formats The Instruction set Memory Addressing Techniques Simply the Architecture & Design of computer System is concerned with the specifications of various functional modules (processors, memories etc), and, structuring them to work as a system.

Micro Operations

A digital system is an inter connection of digital hard ware modules, that accomplish a specific information processing task. Digital modules are defined By the registers they contain, The operations they perform on the data stored in them. The operations executed on the data stored in the internal registers are called as Micro Operations Simply, A Micro Operation is an elementary operation performed on the information stored in one or more registers Some examples can be Load, Clear, Shift, Add.

Register Transfer Language

So, The Internal hard ware organization of a digital computer is best defined by:

The set of registers it contain The sequence of micro operations performed on the contents. The control that initiates the sequence of micro operations

This is possible to specify the sequence of micro operations by explaining in words, but, it would be lengthy description

Register Transfer Language

So its easy to adopt a symbolic language to describe: The sequence of transfers between registers, and Various ALU operations as well The symbolic notation used to describe micro operations is called as Register Transfer Language (RTL) Simply, RTL is a system for expressing in symbolic form the micro operation sequences among the registers of a digital module. RTL is believed to be as simple as possible, so that its easy to organize memorize and use.

Lecture # 02

RTL Basics

Computer registers are designated by capital letters to denote the functionality of the registers. The register, that holds the address of memory is called as Memory Address Register (MAR). Some other examples can be PC,IR, and R etc. The individual bits in an n-bit register are numbered in sequence from (0) to (n-1). Use of displacement Operator, indication of flow of information.

R2 ---- R1

Common way to represent a register is to use rectangular Box, with name inside box.

R1

7 6 5 4 3 2 1 0

15
R2

15
PC(H)

0
PC(L)

If we want the transfer to occur only under a pre-determined Control Condition, that is use of if-then statement. If (P=1) then (R2 ---- R1) P : R2 ---- R1

Every statement written in RTL implies a H/W construction for implementing the transfer. The figure below, shows the block diagram that depicts the transfer from R1 to R2. The (n-outputs) of R1 are connected to (n-inputs) of R2, the (n) will be used to indicate any number of bits for the register. Register has a LOAD input, that is activated by the control variable (P).

Control circuit

load

R2 n R1

clock

As the register operates with clock, it is assumed that (P) is synchronized with same clock. (P) is activated in Control section by rising edge @ time (t), the next transition of clock at (t+1) finds LOAD inputs Active, and , (R2) is loaded with data.

t+1

Transfers occurs here

Final conclusions for RTL

Symbol Letters + numbers Parenthesis

Description denotes a register Part of register

Example MAR, R2 R1(L) R2 (0-7)

Comma

Separates two Micro operations

Lecture # 03

BUS & MEMORY TRANSFERS

A typical digital computer has many registers and paths must be provided to transfer information from one register to another. The number of wires will be excessive, if separate lines are used from each to every other. An efficient scheme for transfer of information b/w multiple registers is Common Bus System. A set of Common lines (one for each bit of a register), which would carry info from different registers.

Use of multiplexers is, given below Multiple Inputs , One Output.

S0

S1

Y
4X1 MUX

0 1 2 3

Use of MUX in Construction of Common Bus

S1 S0
3 2 1 0

M3

M3

M3

M3

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

FIG (1) 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 A

Bus system for Four register, having Four bits each. The bus requires Four multiplexers each having Four inputs, and, one Outputs. Two selection lines, for selecting a particular register as source side.

Bit # (3) from all registers is connected to the (M3) because (M3) is responsible for selecting the bit # (03) of output bus.
Similarly MUX(0), multiplexes the bit #(0) from all registers and provides bit #(0) of output bus.

Bus Selection

Two selection lines (S1) and (S0) are connected to the selection inputs of MUX.

S1 0 0 1 1

S0 0 1 0 1

Register selected A B C D

Function table for bus of fig (1).

GENERALIZING

A bus system will multiplex (K) registers of (n) bits each. The MUX required is (n), having (K) inputs. Finally, transfer of info from bus to any destination register can be done, by connecting bus lines to inputs of all destinations, and activating the LOAD Control (1) (2) BUS ---- C, R1 ---- C R1---- BUS

Lecture # 04

Memory Transfer & Arithmetic Micro Operations

Memory Transfer

The operation of a memory unit is discussed here. The transfer of information from a memory word to the outside environment is called a read operation. The transfer of information to be stored into the memory is called a write operation.

A memory word can be symbolized by letter M.

A specific word is selected by providing memory address during transfer ,&, it is done by enclosing the address in square brackets. A memory unit that receives the add from Address Register (AR) ,called as data transferred to another register, called as data register (DR) is given by, Read: DR ----- M[AR] Write is the reverse of above operation Write: M[AR] ----- R1

Arithmetic Micro Operations

A micro Operation is an elementary operation performed with the data stored in registers. Micro Operations in digital computer can be categorized as:

Arithmetic R-Transfer Logic Shift

The basic arithmetic micro Operations are Addition, Subtraction, Increment and decrement. The Add micro Operation can be defined as; R3 ---- R1+R2

In the above example the contents of R2 are being added in R1 and sum is being placed in R3.

Arithmetic Micro Operations

The increment/decrement micro Operations are symbolized by PLUS/ MINUS ONE. Subtraction is implemented through the Complement and Addition. Instead of using Minus sign, we can write,

R3 ---- R2 - R1
R3 ---- R2 + R1 + 1
Examples:

R3 ---- R1 + R2 R3 ---- R3 R3 ---- R3 + 1 R3 ---- R3 - 1

Binary Adder

In order to implement as micro Operations we need the registers that hold the data and the digital components that perform addition. The digital ckt that forms the sum of two bits and a previous carry is called as Full Adder. The ckt that generates the sum of n-bits binary number is called Binary Adder. A binary adder can be constructed by connecting n full adders in cascade, the output carry from one is feed to input carry of next.

4 Bit Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

FA

C3

FA

C2

FA

C1

FA

C0

C4

S3

S2

S1

S0

Binary Adder Subtractor

The subtractor of binary numbers can be done easily by use of components.

As (A-B) can be done by A+B+1. The ones complement can be implemented by using INVERTERS,and,1 can be then incremented. The addition and subtraction operations can be combined into one common circuit by including an X-OR gate with each full adder. The mode input M is responsible for selecting the operation.

If M=0, the ckt is ADDER.

If M=1, the ckt is SUBTRACTOR.

X-OR Gate
A 0 0 1 1
B 0=B B 1=B Cin=1

B 0 1 0 1

O/P 0 1 1 0
Cin=0

4-Bit Adder Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

FA

C3

FA

C2

FA

C1

FA

C0

C4

S3

S2

S1

S0

Lecture continued

Binary Incrementer

Binary Incrementer

The increment micro operation adds ONE to a number in a register. If a 4 -bit register has a binary value 0110,after, increment its value will be 0111. This operation can be achieved by means of Half Adders.

A= +

1 1

Binary Incrementer

The L.S.D Half Adder is provided the L.S.b of the number to be added, and, the second input is ONE. The output carry from one half adder is connected to the input of next half adder. Ckt receives four bits A3A2A1A0, adds 1 to it, and generates the incremented output in S3S2S1S0. The output carry would be one only, if original number is 1111.

1 1 1 1

+
This 1 is discarded

10 0 0 0

Binary Incrementer

The five bits can not be accommodated so the values are reset. The ckt of the figure given below can be extended to an n-bit Incrementer, by extending diagram to include n half adders.
A3 A2 A1 A0 1 X Y HA x Y HA x Y HA x HA Y

C2 C3 S3 S2

C1

C0

S1

S0

Lecture Continued

Composite Arithmetic Circuit

One composite Arithmetic circuit can be designed to carry out multiple Arithmetic function The basic component is Binary Adder ( parallel ) By controlling the inputs to Parallel Adder, we can obtain different types of operations. Four Full Adders to make Four bit Adder two 4 bit inputs (A) & (B) the Input (A) is provided directly

The second input (B), the, bits are controlled by using MUX The FOUR inputs from (B) are connected with inputs of multiplexers while 2nd input receives the COMPLEMENT OF (B)

The multiplexers also receives two other Inputs as (0) and (1). These four MUX are controlled by using two selection lines (S1) and (S0). The input carry (Cin) goes to the carry input of L.S.B Adder. D= A + Y + Cin A = first input Y=B= second input Cin = input carry = (0 or 1)

By controlling values of (Y) with selection input (S1 and S0), we can perform different operations.

S1
0 0 0 0
1 1 1 1

S0
0 0 1 1 0 0 1 1

Cin
0 1 0 1 0 1 0 1

Y
B B B B 0 0 1 1

D=A + Y + Cin
D=A+B A+B+1 A+B A+B+1 A A+1 A-1 A

WHEN S1S0=11, all 1s are Inserted into Y inputs of F.A, that would be A3A2A1A0 + 1111 But 1111 is actually 2s complement of 1 1111 1 = 1110 = 0001

Lecture # 07

Logic Micro Operations

Logic Micro operations:

Logic Micro Operations specify binary Operations for bits of strings stored in registers. Each bit is considered separately and treated as binary variable. Example of exclusive OR P: R1 -------- R1

R2

When (P = 1), the logic micro operation is to be executed on bits of R1 & R2.

Although the logic micro Operations are not used in scientific computations, but, very important in binary manipulation & Decision making. Special symbols are used to denote different operations, including OR = v AND = ^ Comp = -

By using different symbols, its easy to differentiate between a logic micro Operation and CONTROL Function. Differentiate between the use of +, is is also interpreted as OR operation sometimes, so its better to use special symbols.

P + Q: R1 -------- R2 + R3 , R4 -------- R5 V R6 (OR operation b/w ( Arithmetic ( OR ) P and Q) Plus)

By using two binary variables, 16 different logic micro Operations can be formed, shown in the table. Each of 16 columns ( F0 - F15) represents one possible micro Operation.

Table for the 16 Operations

X Y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15

The 16 Boolean functions of two variables X and Y are expressed in algebraic form below: If X =A, Y =B, then micro Operations are: F0 = 0 F1 = XY F2 = XY F3 = X F4 = XY F5 = Y F6 = X Y F7 = X + Y F15 = 1 F0 F A^B F A^B FA F A^B FB FA B FAvB F0

Hardware Implementation:

The Hardware implementation of logic micro operations requires that LOGIC GATES must be inserted for each bit to perform the required function. The figure below shows one stage of circuit that generates four basic micro Operations. Consists of 4 GATES and a MUX. The output of 4 GATES are applied to the inputs of MUX.

The selection lines choose one of the input and switch it to output, as shown in the diagram.

STAGE OF A Logic CIRCUIT FOR MICRO OPERATIONS

Table for the Output from Selection Lines:

S1 0 0 1 1

S0 0 1 0 1

OUTPUT A^B AvB A B A

APPLICATIONS

Its very useful for manipulating individual bits, or, a portion of register. Change bits, delete and insert. SELECTIVE SET SELECTIVE CLEAR SELECTIVE Comp INSERT MASK --- --- --- OR X - OR AND

Lecture Continued

Shift Micro Operations and Shifter Circuit

Types of Shift Operation

Shift Micro Operations are used for Serial Transfer of Data Can be used in conjunction with Arithmetic and Logic operations as well The information transferred through the serial Input determines the nature of the Shift Operation

3 Broader categories of Shift operation: 1) Logical Shift 2) Circular Shift 3) Arithmetic Shift
Contents can be shifted in Left / Right direction In case of Left Shift, a new bit is introduced at Right most side In case of Right Shift, a new bit is introduced at Left most side

Logical Shift Operation

A logical shift is one that transfers a 0 through the serial Input. Denoted by shl and shr R1-------- shl R1 R2-------- shr R2

The register symbols must be the same on the both sides of displacement operator. Simply, the bit transferred to the END is assumed to be 0

11000011
Example

01100001

showing the Right Shift Operation

Circular Shift Operation

The circular shift is also known as Rotate operation This operation circulates the bits of register around two ends with out the loss of Information Output of the shift register is connected with the Input. Denoted by cil and cir R1-------- cil R1 R2-------- cir R2 The register symbols must be the same on the both sides of displacement operator. Simply, the bit transferred to the END is the Initial bit.

11001100

01100110

Example showing the Right Circular Shift Operation

Arithmetic Shift Operation

An Arithmetic shift, shifts a Signed binary number to left or right

Left Shift means Multiply by 2 Right Shift means Divide by 2

The signed bit remain un changed, bcoz , in multiply/divide the sign of the number is not effected Sign Bit can attain two values

b7=0 b7=1

=== Positive Binary Number === Negative Binary Number (in 2s complement form)

b7

b6

b5

b4

b3

b2

b1

b0

The figure above shows the 8 bit register, b7 contains the SIGN and b6 is the MSB of the binary number.

Arithmetic Shift Operation

b7 b6 b5 b4 b3 b2 b1 b0

b7

b6

b5

b4

b3

b2

b1

b0

0
Example

showing the Right Circular Shift Operation

0
Example

showing the Left Circular Shift Operation

Arithmetic Shift Operation

In case of Arithmetic shift Left, If the New value of b7 is not the same (the value of b7 before the shift operation), AQ sign reversal is indicated. This sign reversal may be interpreted as Over Flow, because Left Shift is actually Multiply with 2 operation. This over flow can be detected by using a Flip Flop such that: Vs= b(n-1) O b(n-2) If Vs=0 ==== No Over Flow If Vs=1 ==== Over Flow occurred

Lecture # 09

Hardware Implementation Of Shift Operations

Hard Ware Implementation:

S

IR
0

H0

IR
A0

H1

IR

A1 A3
0 1

H2

A2

H3
0 1

IL

Hard Ware Implementation:

A combinational Circuit shifter can be constructed as shown above.

Input
S

Output
H
1

The 4 bit shifter has 4 data Inputs AAAA) and 4 data outputs (HHHH)

A0 A1 A2 A3 H
0

H
2

H
3

Two serial Inputs are also provided to accomplish the shift operation

A0 A1 A2 A
3

Ir

A0 A1 A2

IL for Left Shift IR for Right shift

A 0 A 1 A 2 A 3 A 1 A 2 A 3 IL

Lecture # 10

Stored Computer Organization

Stored computer organization

The organization of the computer is best defined by the sequence of micro operations it performs on the data stored in the internal registers. User can control the process by means of a program, as a program is a set of instructions which combine to perform a particular task A computer Instruction is a Binary code that specifies a sequence of micro operations. A program (instructions) are stored in the memory, the computer reads instructions from memory and places it in control register. The control then interprets the Binary code and proceeds to execute it by issuing a Sequence of micro operations.

Stored computer organization

As Instruction code is a group of bits that instruct the computer to perform a specific task, so it must provide:

Operation to be executed The operand to be operated upon

So the Instruction code is broken down into portions,

Operation Code (Op code) Operand

The operation code is actually the group of bits that define several manufacturer defined operations, say Add, And, Clear etc etc. The Number of bits required to represent an Op code depends upon the total number of operations supported by the system.

Indirect Address

Convenient to use the Address bits of an instruction Code not as an ADDRESS, but ACTUAL OPERAND , & Instruction is said to have an Immediate Operand. Address can be

Direct Indirect 14 12 11 0

Opcode

ADDRESS

ADD

457

ADD

457

Operand Operand 1350

+ AC

+ AC

Computer Registers

The Programs9Instructions) are stored in memory and executed one by one. The control reads a instruction from specific address in memory and executes it and son on. This needs a counter, to calculate the address of next instruction to be executed after the current execution is over. A register is also required in control unit for storing the instruction code after it is read from memory. The computer needs processor register for manipulating data and a register for holding memory Address. So the necessary registers are listed below the table.

DR --- 16 AR --- 12 AC --- 16 IR --- 16 PC --- 12 IR --- 16 INPR 8 OUTR 8

Lecture # 11

Computer Instructions

The type of instructions is recognized by the computer control from four bits (15 12). If the O/p bits are not equal to (111) this means MEMORY REFERENCE INSTRUCTION. If the three O/p code bits are (111), then, I bit determine the nature of instruction. If I = 0 ------------ Register reference I = 1 ------------ I/o reference As the instruction is 16-bit long , For . Memory refrence , the last (12) bits are actually Memory Address. xxxx xxxxxxxxxxxx

12 bit address can be represented by there hexa digits

Some Memory reference instructions

Symbol AND ADD LDA STA I=0 0000 0001 0010 0011 I=1 1000 1001 1010 1011

Some register reference instructions

Symbol CLA CLE CMA CME 7800 7400
I opcode 111 Register reference

7200
0

1000

0000

0000

7100

I/O Reference
Symbol INP OUT F800 F400
I 1 opcode 111 Register reference 1000 0000 0000

Before investigating the operations performed by instructions, lets discuss different types of instructions to be included in the Instruction set. A computer should have different instruction available in instruction set so that user may build programs according to requirement.

An instruction set is said to be completer if if contains:

1. 2.

Arithmetic , logical and shift Instructions for moving data from / to memory to/from internal registers

3. 4.

Programs control instructions

Input and output

Lecture # 12

Timing and control

Timing & Control

The timing for all the registers in basic computer is controlled by Master Clock. The clock pulse applied, do not, change the state of the register, unless it is enabled by a control signal. The control signals are generated in control unit & provide control inputs for the MUX in common bus, Micro operations for Accumulator. There are two types of control organization

Hardwired Micro programmed control.

Timing & Control

In the hardwired organization, the control logic is implemented with gates, flip floes & other digital circuits. It can be optimized to produce FAST mode of operation. In case of micro programmed organization, the control information is stored in control memory is programmed to initiate the required sequence of micro operations. A h/w control, as name suggests. It requires changes in the wiring among various components. If the design has to be modified. In micro programmed organization, any required changes can be implemented by updating the program in control memory.

The block diagram for a control unit

Timing & Control

Two decoders & a number of control logic gates. An instruction read from memory is placed in the instruction register (IR). The instruction register is divided into three parts.

I bit (b15) Op Code (b14-b12) Address (b11-b0)

The OP Code in (b14-b12) are decoded with a 3 x 8 decoder.

The 8 outputs of the decoder are denoted by (D7-----D0).

Timing & Control

The sub script value denotes the corresponding OPCODE values. b15 is of the instruction is transferred to a flip-flop designed by I. The bits (b11-b0) are applied to the control logic gates. The 4 bit sequence counter can count from 0 to 15 generating 16 timing signals T0 to T15. The SC counter can be incremented or cleared synchronously, normally it is incremented to provide the sequence of timing signals out of he 4 x 16 decoder. Consider the case where SC is incrementing to provide timing signal T0, T1, T2, T3 & T4.

Timing & Control

At time T4 SC is cleared to ZERO is decoder O/P D3 is activated.

D3T4:SC0

The timing diagram of figure below shows the relationship of control signals. The SC responds to the +ve edge of clock. Initially the CLF is active. The first +ve edge of clock clears SC to ZERO as a result, the timing signal T0 is generated. SC is incremented with every +ve edge of clock, unless its CLR is activated, 15 is produces sequence T0, T1, T2.

Timing & Control

Timing & Control

A memory read/write cycle will be initiated with the rising edge of a timing signal.

T0:ARPC

During the check interval (T0), the contents of PC is placed onto the bus & the load input of AR is enabled.

INSTRUCTION CYCLE:

The program residing in the memory unit of the computer consists of a sequence of instructions. A program is executed in the computer by going through a cycle for each instruction. Each instruction cycle is sub-divided into a sequence of subcycles/phases.

Fetch an instruction from memory. Decode the instruction. Read effective address. Execute the instruction.

Fetch and Decode

Initially PC is loaded with the address of first instruction to be executed. SC generates timing signals T0, T1, T2, T3.

T0: ARPC T1: IR M[AR], PC PC+1 T2: D7-D0 Decode IR(12-14),1 IR(15)

T0: AR PC
Place the contents of PC on bus. Transfer contents from bus to AR by enabling LD input of AR.

Fetch and Decode

T1: IR M[AR], PC PC+1

Enable read output of memory. Place contents of memory on bus. Enable load input of IR Increment PC.

Determine the type of instruction

After decode, the timing signal is T3. During T3, control unit determines the type of instruction that was just read from memory. The flow chart below shows how control determine the instruction type.

Memory reference. Register reference. I/O reference.

The O/P D7 is 1 if OP code (111) & this shows that it is reg/IO reference.
If D7=0, this means it is memory reference.

Determine the type of instruction

Check first bit I

If D7=0 & I=1 (Memory reference with Indirect)

The micro operation for indirect address can be symbolized as

ARM[AR]

The 3 instruction types are sub-divided into four separate paths.

D7IT3: ARM[AR] D7IT3: Nothing D7IT3: I/O reference D7IT3c: Register reference

UNIVERSTITY OF EAST GATE