Timing control in verilog

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Module 3.1 Delays in Verilog

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Procedural blocks and timing controls.

Delay

controls. Event controls. Event controls-Wait

Edge-Sensitive Level-Sensitive

statements.
Named

Events.

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Timing Controls
Delay-Based

Regular delay control AKA Inertial Delay Intra-assignment delay control AKA Transport delay Zero delay control 3/12/13

Regular Delay Control

parameter latency = 20; parameter delta = 2; regx,y,z,p,q; Initial Begin
x=0; // no delay control #10 y = 1; //delay control with a constant #latency z = 0; //delay control with identifier #(latency + delta) p = 1; //delay control with expression #y x = x + 1; //delay control with identifier
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Intra-assignment delay control

Assigning

delay to the right of the assignment operator intra-assignment delay computes the right-hand-side expression at the current time and defer the assignment of the computed value to the left-hand-side variable. to regular delays with a temporary variable to store the current value of a right-hand-side expression
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The

Equivalent

Intra-assignment Delay

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Example 1

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Example 2 : change in assignment

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Example 3 : Ex1 + change in assignment

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Zero delay control

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Zero delay control

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Timing Control
Verilog

is a discrete event time simulator. If there is no timing control, simulation time does not advance. Simulated time can only progress by one of the following:

gate or wire delay, if specified a delay control, introduced by the # symbol. an event control, introduced by the @ symbol. the wait statement.
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The

Delay based Timing Control

Delay

Control (#)

Expression specifies the time duration between initially encountering the statement and when the statement actually executes. Delay in Procedural Assignments
Inter-Statement Intra-Statement

Delay Delay Delay Delay

For example:
Inter-Statement

#10 A = A + 1;
Intra-Statement

A = #10 A + 1;

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Event-Based Timing Control (cont.)

Events

(@)

Change in the value of a register or net Used to trigger execution of a statement or block (reactive behavior/reactivity)

Types

of Event-based timing control

Regular event control Named event control Event OR control
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Event-Based Timing Control (cont.)

Regular

event control

Symbol: @(<event>) Events to specify:

posedge

sig:

Change of sig from any value to 1 or from 0 to any value

negedge

sig:

Change of sig from any value to 0 or from 1 to any value

sig:

Any chage in sig value

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Event-Based Timing Control (cont.)

Regular

event control Examples:

@reg_a begin A = B&C; end

@(posedge clock1) A = B&C;

@(negedge clock2) A = B&C;

Forever @(negedge clock3) begin

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Event-Based Timing Control (cont.)

Named

event control

You can declare (name) an event, and then trigger and recognize it. Verilog keyword for declaration: event
event

event1;

Verilog symbol for triggering: ->

->event1

Verilog symbol for recognizing: @()

@(event1)

begin

<some procedural statements> 3/12/13

end

Event-Based Timing Control (cont.)

Event

OR control

Used when need to trigger a block upon occurrence of any of a set of events. The list of the events: sensitivity list Verilog keyword: or Look at the handout

Event

OR control Example:

always @ ( reset or clock )

begin if ( reset ) q= 1b0; else 3/12/13

Timing Control (cont.)

wait

Statement

The wait statement allows a procedural statement or a block to be delayed until a condition becomes true. The difference between the behavior of a wait statement and an event is that the wait statement is level sensitive whereas @(posedge clock); is triggered by a signal transition or is edge sensitive. For Example:
wait

(A == 3)
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begin

Delay Back-Annotation
Delay back- annotation is an important and vast topic in timing simulation. in this section, we introduce the designer to the concept of backannotation of delays in a simulation.

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The various steps in the flow that use delay back-annotation are as follows: 1. The designer writes the RTL description and then performs functional simulation. 2. The RTL description is converted to a gate level netlist by a logic synthesis tool. 3. The designer obtains prelayout estimates of delays in the chip by using a delay calculator and information about the IC fabrication process. Then, the designer does timing simulation or static timing verification of the 3/12/13 gate-level netlist, using these preliminary

4. The gate-level netlist is then converted to layout by a place and route tool. The postlayout delay values are computed from the resistance (R) and capacitance (C) information in the layout. The R and C information is extracted from factors such as geometry and IC fabrication process. 5. The post-layout delay values are backannotated to modify the delay estimates for the gate-level netlist. Timing simulation or static timing verification is run again on the gate-level netlist to check if timing constraints are still satisfied.
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Delay Back-Annotation

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