HIGH LEVEL SYNTHESIS

Presented By J.Jasper Beusan Jeny N.Kowsalya Devi

What is High Level Synthesis?

It is the process of mapping a behavioral description at algorithmic level to a structural description in terms of functional units, memory elements and interconnections. Functional units implement one or more elementry operations like addition multiplication etc.

HARDWARE MODELS FOR HIGH LEVEL SYNTHESIS The outputs which only depends on current inputs is called combinational circuits. The output which not only depends on the present value but on the past history of its inputs is called sequential circuits. Sequential circuits are divided into two types - Synchronous or Clocked circuits

- Asynchronous circuits
All High Level Synthesis system restrict the model to Synchronous Circuits.

Hardware for Computations, Data storage, and Interconnection

The essential hardware components are - Functional Units

- Registers
- Multiplexer - Bus - 3 state Driver

Hardware for Computations, Data storage, and Interconnection

Functional Unit Realizes some Boolean functions such as Adder, Multiplier or an ALU. Registers To store data in the circuit. Multiplexers Depending on the value of control signals the output becomes equal to one of the inputs.

Buses Many components are connected to the bus for reading and writing.
Tri-state Buffer Depending on the enable signal Tri-state driver either connects its input to its output or puts the output in high impedance state.

Data, Control and Clocks

Signals in a Logic Circuit is divided into two groups - Data Signals: It carry the operands of the functional units - Control Signals: It regulates the transfer of data signals between hardware components The hardware component interconnected by wires carrying data signals called as data path Multicycle operations occupy an FU for total duration of computation

Data, Control and Clocks(Cont..)

Performing more than one computation in one clock cycle is called Pipelining. When FU is pipelined, it can receive a new input before the output of the previous input is produced.

In two-phase clocks one part of the operation is performed in one clock phase and the other part in second clock phase.

Internal Representation of the Input Algorithm

The algorithm is synthesized by Hardware Description Languages such as Verilog,VHDL and Silage.

The graph that is used to represent an algorithm is called Data Flow graph(DFG).
DataFlow Graph Control Flow Graph

Two types of graphs

Simple Data Flow

Dataflow graph is a directed graph G(V, E). Set of nodes V is subdivided as computational nodes. Input and output nodes for communication ,conditional nodes for decision making. Computational nodes are either atomic or composite atomic nodes - elementary computations

composite nodes - representation of hierarchy

Simple DFG

Different Stages of Execution

CONDITIONAL DATA FLOW

2 special nodes
Selector node Distributor node

 Both are characterized by a horizontal input Can carry only Boolean tokens
Produced by computational nodes e.g. perform a comparison as less than or equal to

Selector node has two input labels

True False

Distributor node has two output labels

True false

 FIRING RULES:
In case of selector node

 In case of distributor node

 Conditional nodes can be used to represent if-thenelse constructs. An example of a conditional construct

if a b , c a b; else c b a;

 DFG representation of the program fragment

ITERATIVE DATA FLOW

Combination of selector and distributor nodes can be used for the representation of iterative constructs. An example of iterative constructs with simple while loop while (a>b)

a a b;

 DFG representation of the program

 An initial token with value false has to be present at the horizontal input of the selector node in order to allow the computation to start. Cycle in DFG can produce deadlock- none of the nodes in the cycle can fire as each node is waiting for the predecessor in the graph. Input values that arrive at regular intervals in DFG introduce synchronous behavior but that are asynchronous by nature. Output values not only depend on current inputs but also previous one.

 Synchronous token flow

 By using separate delay node

This node stores an incoming for a period T0 ,the iteration period of the graph. After this period the token is passed to the output.

 DFG of a second order digital filter design

DATA FLOW GRAPH REPRESENTATION

Inputs and output nodes need to be distinguished. Cell-port-net model is not suitable because DFG always connect two ports but nets can connect to multiple ports. So node-port representation is best.

 DFG of Node-port representation

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