BI-CMOS TECHNOLOGY

B LOKESHWAR ASST PROFESSOR RVR and JC College of Engineering

BJT AND CMOS

BJT Characteristics

Higher Switching Speed High current drive per unit area, Higher gain Better Noise Performance Better High Frequency Characterstics High Power Dissipation Low Input Impedance(High Driving Capability) High Output Impedance Low Packing Density

BJT AND CMOS(CONT)

CMOS Characttristics

Low Power Dissipation Higher Noise Margins Higher Packing DensityLower Manufacturing Cost per Device High Input Impedance(Low Driving Capability) Low Output Drive Current Bi Directional Capability A near Ideal Switch Speed is the only restricting factor, especially when large capacitors must be driven

COMPARISON BJT AND CMOS

BJT Low Input Impedance(High Drive Current) Lower Packing Density CMOS High Input Impedance(Low Drive Current) Higher Packing Density

High Transconducatance
Lower Noise Margins Higher Power Dissipation Unidirectional Capability No Lower Switching Speed

Low Transconducatance
Higher Noise Margins Lower Power Dissipation Bidirectional Capability A near Ideal Switch Higher Switching Speer

BI CMOS ADVANTAGES
By combining the two technologies BiCMOS offers the following advantage: Lower power dissipation than bipolar Improved speed in comparison to CMOS Larger current drive than CMOS Disadvantages: Higher cost Larger fabrication time ( more mask steps)

NOTE:
CMOS has an advantage over bipolar in the areas of lower power dissipation, larger noise margins, and greater packing densities, while bipolar has advantages over CMOS in faster switching speed and larger current capability

BICMOS LOGIC
BiCMOS is a complex processing technology that provides both NMOS and PMOS devices, as well as npn and pnp bipolar transistors High input impedance logic gates (that require little drive current) are provided by the MOSFETs, and high current drive can be provided from the BJTs due to their high current gain and transconductance

BI CMOS INVERTER

BICMOS INVERTER (WHEN INPUT IS LOW)

Case I: When VI=logic 0 The MN and Q2 are off while Mp conducts, which forces Q1 on. TheQ1 then provide a large output current to charge the load capacitance. The result is very short low-to-high propagation delay time. Q1 is essentially acts as a pull up transistor and V0(max)=VDD-VBE1(on)

BICMOS INVERTER (WHEN INPUT IS HIGH)

Case II: when VI = logic 1 Mp goes off, MN and Q2 turn on. The transistor Q2 provide large output current that quickly discharge the load capacitor, which result a short high to low propagation delay time. The output voltage continue to decrease until VO(min)=VBE2(on),

INTRODUCTION

By combining the two technologies BiCMOS offers the following advantage:

Low power dissipation comparable to CMOS Improved speed comparable to TTL or ECL technology Large current driving capability comparable to TTL or ECL Large noise margin similar to TTL technology

BI CMOS INVERTER

QUESTION :

QUESTION 1:

QUESTION 2:

QUESTION 3:

ANSWER FOR Q3