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Logic Synthesis
VHDL description
architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;
Circuit netlist
Scripts
/* Directory configuration */
foreach (block, blocks) { block_source = src_directory + block + ".vhd" read_file -format vhdl -rtl block_source analyze -format vhdl -lib WORK block_source }
current_design block /* All commands now apply to the entity "exam1" */
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The name of each file should be exactly the same as the name of an entity or package it contains. Arrange entity names in the bottom-up order (the top-most entity at the end of the list) and define this list in your script using the command
blocks = { entity1, entity2, , entityN}
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Use an identical name for the clock signal in all your entities and packages (including declarations of components).
Use the same clock name in all clock-related commands of your script, such as create_clock, set_clock_transition, etc.
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Place all your synthesizable source files in the vhdl directory, and your testbench files in the tb directory. Place your scripts in the script directory. Define at least the following directories close to the beginning of your script:
src_directory, report_directory, db_directory.
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Please do your best to eliminate all errors and majority of warnings generated by the scripts and written to the log files.
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Results of synthesis
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Combinational area: 10593.477539 Noncombinational area: 14295.521484 Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: Total area:
ECE 545 Introduction to VHDL
24888.976562 undefined
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clk
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n+m n+m
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Clock Jitter
Rising Edge of The Clock Does Not Occur Precisely Periodically
May cause faults in the circuit
clk
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Clock Skew
Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time
in D Q D Q out
clk
delay
in
out
delay
ECE 545 Introduction to VHDL
clk
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0.00 0.12 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10
2.03 f 2.15 f 2.25 f 2.34 f 2.44 f 2.54 f 2.63 f 2.73 f 2.82 f 2.92 f 3.02 f 3.11 f 3.21 f 3.31 f 3.40 f 3.50 f
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0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10
3.60 f 3.69 f 3.79 f 3.88 f 3.98 f 4.08 f 4.17 f 4.27 f 4.37 f 4.46 f 4.56 f 4.66 f 4.75 f 4.85 f 4.94 f 5.04 f 5.14 f
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Timing parameters
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Timing parameters
definition delay time pointpoint rising edge rising edge of clock 1 clock period
units
ns ns MHz
pipelining
clock period
clock frequency
good good
latency
time inputoutput
ns
bad
throughput
Mbits/s
good
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multiplexer
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M2
C1
M3
IN
C2
OUT
Latency k clock_period
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round 1
Throughput =
target clock period, e.g., 20 ns
...
round 16
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Optimization criteria
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speed
area
power
testability
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latency area
throughput
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Optimization methods
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