Assembly language programming

Lecture 6, 7

Structure of an assembly language program

The architecture of a processor is the assembly language programmers view of it Architecture is made up of the processors register, its instruction set, and its addressing modes Structure of an assembly language program is composed of both instructions and commands assembler directives

Structure of an assembly language program

ORG $400 MOVE P,D0 ADD Q,D0 MOVE D0,R STOP #$2700

*
P Q R ORG DC.W DC.W DS.W END $500 2 4 1 $400

Structure of an assembly language program assembler directives

Assembler statements can be divided into two types: executable statements and assembler directives An executable statements is an instruction in mnemonic form that the assembler translates into the machine code of the target microprocessor MOVE P,D0 ADD Q,D0 MOVE D0,R STOP #$2700

Structure of an assembly language program assembler directives

An assembler directive tells the assembler something it needs to know about the program it is assembling:
E.g., the assembler directive ORG means origin and tells the assembler where the instructions or data are to be loaded in memory The expression ORG $400 tells the assebler to load instruction in memory starting at address 40016 The value of 40016 is used because the 68K reserves the first 1024 bytes of memory in locations 0 to 3FF16 for a special purpose

Structure of an assembly language program assembler directives

1 2 3 4 5 6 7 8 9 10 11
Line number

00000400 00000400 00000406 0000040C 00000412 00000500 00000500 00000502 00000504

Address or memory location

303900000500 D07900000502 33C000000504 4E722700 *

0002 0004 00000002 00000400
Operand or contents of memory

ORG MOVE ADD MOVE STOP ORG P: Q: R: $500 DC.W DC.W DS.W END
Mnemonic or assembler Directive field

$400 P,D0 Q,D0 D0,R #$2700

2 4 1 $400
Operand field

The label field

Structure of an assembly language program assembler directives

As you can see the instruction MOVE D0,R is located on line 4 and is stored in memory location 40C16 This instruction is translated into the machine code 33C00000050416, where the operation code is 33C016 and the address of operand R is 0000050416

Structure of an assembly language program assembler directives

The assembler maintains a variable, called the location counter, that keeps track of where the next instruction or data element is to be located in memory When one writes ORG directive, the location counters value is preset to that specified by the ORG.

Structure of an assembly language program assembler directives

The define constant assembler directive, DC, allows you to load a constant in memory (i.e. it provides means of presetting memory locations with data before a program is executed) This directive is written DC.B to store a byte, DC.W to store a word, and DC.L to store a longword

Structure of an assembly language program assembler directives

In the example ORG $500 P: DC.W 2 a programmer places the value 2 in memory, and labels the location P Since the directive is located immediately after the ORG $500 assembler directive, the integer 2 is located at memory location 50016 This memory location (i.e. 50016) can be referred to as P (MOVE P,D0) Because the size of the operand is a word, the value 0000 0000 0000 00102 is stored in location 50016

Structure of an assembly language program assembler directives

The next assembler directive Q: DC.W 4 loads the constant 4 in the next available location 50216 The define storage directive, DS, tells the assembler to reserve memory locations and also takes a .B, .W, or a .L qualifier For example DS.W 1 tells the assembler to reserve a word in memory and to equate the address of the first word with R

Structure of an assembly language program assembler directives

The difference between DC.B N and DS.B N is that the former stores the 8-bit value N in memory, whereas the latter reserves N bytes of memory by advancing the location counter by N The final assembler directive, END $400, tells the assembler that the end of the program has been reached and that there is nothing else left to assemble

Structure of an assembly language program assembler directives

Another important assembler directive is EQU, which equates a symbolic name to a numeric value. For example, in case of Tuesday EQU 2 one can use the symbolic name Tuesday instead of its value, 2. Statements ADD #Tuesday,D0 and ADD #2,D0 are identical

Example of drawing a memory map

Size Width Perim
ORG DC.B DC.B DS.B ORG MOVE.B ADD.B ADD.B MOVE.B STOP END $1000 25 14 1 $1200 Size,D0 Width,D0 D0,D0 D0,Perim #$2700 $1200

Example of drawing a memory map

$1000 25 Size

$1001 $1002

14

Width Perim

Data area

$1200 $1204 $1208 $120A $120E $1212

MOVE.B Size,D0 ADD.B Width,D0 ADD.B D0,D0 MOVE.B D0,Perim STOP #$2700 Program area

Example of drawing a memory map: relationship between a source program, assembled program, and memory map

1 2 3 4 5 6 7 8 9 10 11

00001000 00001000 00001001 00001002 00001200 00001200 00001204 00001208 0000120A 0000120E

19 0E 00000001 10381000 D0381001 D000 11C01002 4E722700 00001200

Size Width Perim

ORG DC.B DC.B DS.B ORG MOVE.B ADD.B ADD.B MOVE.B STOP END

$1000 25 14 1 $1200 Size,D0 Width,D0 D0,D0 D0,Perim #$2700 $1200

Example of drawing a memory map: relationship between a source program, assembled program, and memory map

This program uses two define-constant directives to set up constants called Size and Width in memory These two constants are 25 and 14, which are represented in hexadecimal as $19 and $0E, respectively These two define-constants are 1-byte directives each and hence are loaded at addresses $1000 and $1001, respectively The define-storage assembler directive, Perim DS.B 1, reserves a one-byte location called Perim at $1002

Example of drawing a memory map: relationship between a source program, assembled program, and memory map

The second ORG directive resets the assemblers location counter to $1200 The first instruction, MOVE.B Size,D0, copies the contents of memory location Size to data register D0 The next instruction adds the contents of memory location Width to the contents of D0 The result is then doubled The operation MOVE.B D0,Perim copies the result into the memory location Perim

Operand size and the 68K

The 68K has a 32-bit architecture and a 16-bit organization The sizes of operands assembler programmer operates with is important The 68K has a byte-addressable architecture. Successive bytes in memory are stored at consecutive byte addresses (0,1,2,3) and any byte in memory can be individually read from or written to In case if 16-bit word is sent down to memory, then successive words are stored at consecutive even addresses: 0,2,4,6 32-bit longwords are stored at addresses 0,4,8,...

Operand size and the 68K

8 bits (1byte) 1000 1001 1002 1003 1004 1005 1006 1000 1002 1004 1006 1008 100A 100C 16 bits (1 word) 1000 1004 1008 100C 1010 1014 1018 32 bits (1 longword)

1007
1008 1009 100A 100B

100E
1010 1012 1014 1016

101C
1020 1024 1028 102C

Operand size and the 68K

If one stores a 32-bit longword at memory location $1000, the most-significant byte of an operand goes to the lowest address E.g., when longword $12345678 is stored, byte $12 goes to the address $1000 This storage order is called Big-Endian Intel processors are Little-Endian and store bytes in the reverse order to the 68K family

Operand size and the 68K

All addresses processed and stored by the 68K are 32-bit values. However, not all 32 address lines are connected to pins. Addresses from 24 to 31 are not connected to the pins and hence cannot be used to access memory The 68Ks address bus is effectively 24 bits wide and can access only 2^24 bytes (16 Mbyte) of addressable memory Later members of the 68K family support a full 32-bit wide address bus and a 2^32 byte (4GByte) address space

The 68Ks registers

The 68K has a register-to-memory architecture and therefore it needs registers to be able to access memory The 68K has eight 32-bit general-purpose data registers, eight 32-bit address registers, an 8-bit condition code register, an 8-bit status byte, and a 32bit program counter The status byte is only accessed by the operating system and is invisible to the user programmer because it simply defines the 68Ks operating mode and controls the way in which interrupts are dealt with

The 68Ks registers

d31 d16 d15 d08 d07 d00
D0 D1 D2 D3 D4 D5 D6 D7 a31 a16 a15 a08 a07 a00 A0 A1 A2 A3 A4 A5 A6 A7

PC
X N Z V C CCR

Data registers
The 68K has eight general-purpose data registers, numbered D0 to D7 Any operation that can be applied to data register Di can also be applied Dj There are no special purpose data registers reserved for certain types of instruction When a byte operation is applied to the contents of a data register, only bits D00 to D07 of the register are affected, similarly, a word operation affects bits D00 to D15. Only the lower-order byte (word) of a register is affected by a byte (word) operation

Data registers
For example, applying a byte operation to data register D1 affects only bits 0 to 7 and leaves bits 8 to 31 unchanged. CLR.B D1 forces the contents of D1 to XXXX XXXX XXXX XXXX XXXX XXXX 0000 0000

Address registers
The 68K has eight 32-bit address registers, called A0 to A7, which act as pointer registers Registers A0-A6 are identical in that whatever we can do to Ai, we can also do to Aj. Address register A7 has an additional function of being used as a stack pointer for the storage of subroutine addresses Operations on address registers do not affect the 68Ks condition code register

Address registers
The contents of an address register is considered to be a single entry, byte and word divisions of address registers are meaningless All operations on an address register are longword operations .W operations are automatically extended to .L Addresses are treated as signed twos complement values. If we perform operation on the lower-order word of an address register, the sign bit is extended from A15 to bits A16 to A31.

Address registers
For instance the operation
MOVEA.W #$8022,A3

has the effect [A3]<-$FFFF8022 Similarly, the operation

MOVEA.W #$7022,A3

has the effect [A3]<-$00007022

Address registers
Positive and negative addresses can seem strange but in fact positive address can be thought of meaning forward and negative address meaning backward E.g., A1 contains the value 1280 and A2 contains the value 40 (stored as the appropriate twos complement value). Adding the contents of A1 to the contents of A2 by ADDA.L A1,A2 to create a composite address results in the value 1240, which is 40 locations back from the address pointed at by A1

The 68Ks instruction set: data movement instructions

Typical 68K data and address movement instructions are:
MOVE Di,Dj
[Dj]<-[Di]

MOVE P,Di
[Di]<-[M(P)]

MOVE Di,N
[M(N)]<-[Di]

EXG Di,Dj
[Temp]<-[Di],[Di]<-[Dj],[Dj]<-[Temp]

SWAP Di
[Di(0:15)]<-[Di(16:31)],[Di(16:31)]<-[Di(0:15)]

LEA P,Ai
[Ai]<-P

The 68Ks instruction set: data movement instructions

The EXG instruction exchanges the contents of two registers (its intrinsically a lognword operation). EXG may be used to transfer the contents of an address register into a data register and vice versa. SWAP exchanges the upper- and lower- order words of a given data register. The LEA (load effective address) instruction generates an address and puts it in an address register

The 68Ks instruction set: arithmetic and logical operations

Arithmetic operations are those that act on numeric data (i.e. signed and unsigned integers) Simple example is ADD M,Di Other arithmetic operations implemented by the 68Kare SUB (subtract), DIVU, DIVS (unsigned and signed divide), MULU and MULS (unsigned and signed multiply), and NEG (negate) The 68Ks logic (i.e. Boolean) operations AND, OR, EOR, NOT act on the individual bits of a word, whereas arithmetic operations act on the whole number

The 68Ks instruction set: shift operations

Shift operation moves a group of bits one or more places left or right. Shift operations in the 68K can be applied by bytes, words and longwords Example:
logical shift by one place right, LSR, of the 8-bit value 1100 1010 will give: 0110 0101 arithmetic shift treats the data shifted as a signed twos complement value and the value of 1100 1010 (-54) after arithmetic shift right, ASR, will become 1110 0101 (-27)

The 68Ks instruction set: shift operations Logical shift left

LSL C X

Operand

(a 0 enters the least-significant bit and the mostsignificant bit is copied to the C and X flags in the CCR
Logical shift right (a 0 enters the most-significant bit and the leastsignificant bit is copied to the C and X flags in the CCR

LSR 0 Operand C X

The 68Ks instruction set: shift operations Arithmetic shift left

ASL C X

Operand

(a 0 enters the least-significant bit and the mostsignificant bit is copied to the C and X flags in the CCR
Arithmetic shift right (the old mostsignificant bit is copied into the new most-significant bit and the leastsignificant bit is copied to the C and X flags in the CCR

ASR MSB Operand C X

The 68Ks instruction set: circular shifts and rotates

A circular shift or rotate treats the data being shifter as a ring with the most-significant bit adjacent to the least-significant bit Circular shifts result in the most-significant bit being shifted into the least-significant bit position (left shift), or vice versa for a right shift No data is lost during a circular shift The 68K supports two types of circular shift of the bits of a register: rotate left (ROL) and rotate right (ROR)

The 68Ks instruction set: circular shifts and rotates

The bit that is shifted out at one end is shifted into the other end and also copied into the carry bit Example:
Initial D0 11001110 11001110 11110000 Shift ROL.B #1,D0 ROR.B #1,D0 ROL.B #2,D0 D0 after the shift 10011101 01100111 11000011

The 68Ks instruction set: circular shifts and rotates

ROL

Operand

Rotate left the most-significant bit is copied into the leastsignificant bit and the carry flag Rotate right the least-significant bit is copied into the mostsignificant bit and the carry flag

ROR Operand C

The 68Ks instruction set: circular shifts and rotates

ROXL C

Operand

Rotate left through extend the most-significant bit is copied into the X and C flags in the CCR and the old X bit into the leastsignificant bit

ROXR
X Operand C

Rotate right through extend the least-significant bit is copied into the X and C flags in the CCR and the old X bit into the mostsignificant bit

The 68Ks instruction set: circular shifts and rotates

In figure, one can see the 68Ks two circular shift operations that include the extend bit (X-bit) in the condition code register The mnemonics for these instructions are ROXL and ROXR (rotate left through extend and rotate right through extend)

The 68Ks instruction set: logical operations and branching

Like shift operations, logical operations allow you to directly manipulate the individual bits of a word. The 68K implements four logical operations: NOT, AND, OR, and EOR. NOT inverts the bits of an operand:
[D0]=11001010, the operation NOT.B D0 results in [D0]=00110101

The 68Ks instruction set: logical operations and branching

The AND operation is dyadic and is applied to a source and destination operand. Bit i of the source is AND-ed with bit i of the destination and the result is stored in bit i of the destination
If [D0]=1100 1010, operation AND.B #%1111 0000, D0 results in [D0]=1100 0000

The AND operation is used to mask the bits of a word

If one AND bit x with bit y, the result is 0 if y=0 and x if y = 1.

The 68Ks instruction set: logical operations and branching

The OR operation is used to set one or more bits of a word to 1. ORing a bit with 0 has no effect, and ORing the bit with 1 sets it.
if [D0]=1100 1010, the operation OR.B #%1111 0000, D0 results in [D0]=1111 1010

The EOR operation is used to toggle one or more its of a word. EORing a bit with 0 has no effect, and EORing it with 1 inverts it.
if [D0]=1100 1010, the operation EOR.B #%1111 0000, D0 results in [D0]=0011 1010

The 68Ks instruction set: logical operations and branching

By using the NOT, AND, OR, and EOR instructions, you can perform any logical operations on a word. Suppose you wish to clear bits 0, 1, and 2, set bits 3, 4, and 5, and toggle bits 6 and 7 of the byte in D0: AND.B #%1111 1000, D0 clear bits 0, 1, and 2 OR.B #%0011 1000, D0 set bits 3, 4, and 5 EOR.B #%1100 0000, D0 toggle bits 6 and 7

The 68Ks instruction set: logical operations and branching

A branch instruction modifies the flow of control and causes the program to continue execution at the target address specified by the branch. The simplest branch instruction is the unconditional branch instruction, BRA target that always forces a jump to the instruction at the target address.

The 68Ks instruction set: logical operations and branching

In the following example, the BRA Here instruction forces the 68K to execute next the instruction on the line which is labeled by Here BRA Here . . . Here MOVE D0, D4 The 68K provides 14 conditional branch instructions of the form Bcc, where cc is one of 14 possible combinations

The 68Ks instruction set: logical operations and branching

Mnemonic BCC BCS BEQ BNE BGE BGT BHI BLE BLS BLT BMI BPL BVC BVS Instruction branch on carry clear branch on carry set branch on equal branch on not equal branch on greater than or equal to branch on greater than branch on higher than branch on less than or equal to branch on lower than or same branch on less than branch on minus branch on plus branch on overflow clear branch on overflow set Branch on condition C C Z Z N V + N V N V Z + N V Z C Z Z + N V + N V C+Z N V + N V N N V V

The 68Ks instruction set: logical operations and branching

Conditional branch instructions test one or more bits of the CCR. If the result of the test is true, a branch is made to the target address. Otherwise the instruction following the branch is executed. Without branch instructions we would not be able to implement high-level language constructs such as IFTHENELSE or DOWHILE

The 68Ks instruction set: logical operations and branching

When the CPU executes most instructions, CCRs flag bits are automatically updated. Each flag bit in the CCR may be set by an instruction, cleared by it, or remain unaffected. The Z-bit is set if the result of an operation yields a zero result. The N-bit is set if the most-significant bit of the result is one. The carry bit is set if the carry out of the most-significant bit of the result is one. The V-bit is set if the operation yields an out of range result when the operand(s) and result are all regarded as twos complement values

The 68Ks instruction set: logical operations and branching

Remember that for the purpose of setting or clearing bits of the CCR, the term mostsignificant bit refers to bit 7, 15, or 31, depending on whether the current operation is a byte, word, or longword operation, respectively. You can also directly modify the contents of the CCR by special instructions like MOVE #N,CCR

The 68Ks instruction set: logical operations and branching

As shown, some branch instructions test a single bit in the CCR, whereas others test two or three bits. Some test are applied to unsigned numbers and some to signed numbers. Consider the numbers P=1111 0000 and Q=0011 0000. If these numbers are unsigned, P=240 and Q=48, and P>Q. If these numbers are regarded as signed, P=-16 and Q=48, and P<Q. If we wish to branch on > we would use BGT with signed numbers and BHI with unsigned numbers.

The 68Ks instruction set: logical operations and branching

The target address used by a branch instruction is automatically calculated by the assembler. All that needs to be written is Bcc <target> and then label the appropriate target instruction with <target>. Consider the following example: ADD D1, D2 add D1 to D2 and branch IF the result is minus BMI ERROR ELSE part ERROR ... THEN part

The 68Ks instruction set: logical operations and branching

ADD D1, D2 BMI BRA ... ERROR ELSE part EXIT Skip past the THEN part THEN part add D1 to D2 and branch IF the result is minus

ERROR EXIT The unconditional branch instruction BRA EXIT forces the computer to execute the next instruction at EXIT and skips past the ERROR clause.

The 68Ks instruction set: logical operations and branching

Lets now look at more detailed example on conditional behavior. Example is a subroutine to convert a 4-bit hexadecimal value into its ASCII equivalent.

The 68Ks instruction set: logical operations and branching

ASCII character 0 1 2 3 Hexadecimal value 30 31 32 33 Binary value 0000 0001 0010 0011

4
5 6 7 8 9 A B C D E F

34
35 36 37 38 39 41 42 43 44 45 46

0100
0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

The 68Ks instruction set: logical operations and branching

For example, if the internal binary value in a register is 0000 1010, its hexadecimal equivalent is A16. In order to print the letter A on a terminal, one has to transmit the ASCII code for the letter A (i.e. $41) to it. Note the difference between the internal binary representation of a number within a computer and the code used to represent the symbol for that number.

The 68Ks instruction set: logical operations and branching

Number six is expressed in eight bits by the binary pattern 0000 0110 and is stored in the computers memory in this form. On the other hand, the symbol for a six (i.e. 6) is represented by the binary pattern 0011 0110 in the ASCII code. If we want a printer to make a mark on paper corresponding to 6, we must send the binary number 0011 0110 to it. All numbers held in the computer must be converted to their ASCII forms before they can be printed.

The 68Ks instruction set: logical operations and branching

We can now derive an algorithm to convert a 4bit internal value into its ASCII form. A hexadecimal value in the range 0 to 9 is converted into ASCII form by adding hexadecimal 30 to the number. A hexadecimal value in the range $A to $F is converted to ASCII by adding hexadecimal $37.

The 68Ks instruction set: logical operations and branching

If we represent the number to be converted by HEX and the number to be converted by ASCII, we can write down a suitable algorithm in the form IF HEX<$A THEN ASCII := HEX + $30 ELSE ASCII := HEX + $37 Alternatively, we can rewrite the algorithm as ASCII := HEX + $30 IF ASCII>$39 THEN ASCII:=ASCII+7

The 68Ks instruction set: logical operations and branching

The alternative algorithm can be translated into low level language as ADD.B #$30,D0 ASCII:=HEX+$10 CMP.B #$39,D0 IF ASCII<39 THEN EXIT BLE EXIT ADD.B #7, D0 ELSE ASCII:=ASCII+7 EXIT RTS Assumptions made: D0.B holds a HEX value on subroutine entry; D0.B holds the ASCII character code on return; no other register is notified by this subroutine

The 68Ks instruction set: logical operations and branching

Using instruction CMP source, destination leads to the effect of subtracting the source operand from the destination operand and then set the flag bits of the CCR accordingly. CMP is the same as SUB except that the result is not recorded.

The 68Ks instruction set: logical operations and branching

Example: * * IF x=y THEN y=6 IF x>y THEN y=y+1 CMP.B D0,D1 BNE NotEqu MOVE.B #6,D1 BRA exit BGE exit ADD.B #1,D1
Assume that x is in D0 and y in D1 IF x=y THEN y=6 and leave the algorithm IF x<=y THEN exit ELSE y=y+1 exit point for the algorithm

NotEqu exit

The 68Ks instruction set: logical operations and branching

Note that we perform two tests after the comparison CMP.B D0,D1. One is a BNE and the other is BGE. We can carry out the two tests in succession because no intervening instruction modifies the state of the CCR. Although the conditional test performed by a highlevel language can be quite complex (e.g. IF X+YZ>3t), the conditional test at the assembly language level is rather more basic, as this example demonstrates

The 68Ks instruction set: templates for control structures

We can readily represent some of the control structures of high-level languages as templates in assembly language. A template is a pattern or example that can be modified to suit the actual circumstances. In each of the following examples, the high-level construct is provided as a comment. This condition tested is [D0]=[D1] and the actions to be carried out are Action1 or Action2. The aim of templates is to provide the appropriate test instead of CMP D0,D1 and provide the appropriate sequence of assembly language statements instead of Action1 or Action2.

The 68Ks instruction set: templates for control structures

* * IF [D0]=[D1] THEN Action1
perform test IF [D0]<>[D1] THEN exit

CMP D0,D1 BNE EXIT Action1 ... ... EXIT

Exit point for construct

The 68Ks instruction set: templates for control structures

* * IF [D0]=[D1] THEN Action1 ELSE Action2 CMP D0,D1 Compare D0 with D1 BNE Action2 IF [D0]<>[D1] perform ... ... BRA EXIT Skip round Action2 ... Action2 ...

Action2

Action1

Action2 EXIT

Exit point for construct

The 68Ks instruction set: templates for control structures

* * * * FOR K=1 TO J ... ENDFOR MOVE #1,D2 ... ... ADD #1,D2 CMP #J+1,D2 BNE Action1
Load loop counter, D2, with 1

Action1

Perform Action1

Increment loop counter Test for end of loop

IF not end THEN go round again ELSE exit

EXIT

The 68Ks instruction set: templates for control structures

* WHILE [D0]=[D1] Perform Action1 * Repeat CMP D0,D1 Perform test BNE Exit If [D0]<>[D1] THEN Exit Action1 ... Else carry out Action1 ... BRA Repeat REPEAT loop EXIT Exit from construct

The 68Ks instruction set: templates for control structures

* REPEAT Action1 UNTIL [D0]=[D1] * Action1 ... Perform Action1 ... CMP D0,D1 Carry out test BNE Action1 REPEAT as long as [D0]<>[D1] EXIT Exit from loop

The 68Ks instruction set: templates for control structures

* * * * * * * * * CASE OF I I=0 Action0 I=1 Action1 I=2 Action2 I=3 Action3 ... I=N ActionN I>N Exception
CMP.B
BGT MOVE.W MULU LEA LEA MOVEA.L JMP * Table Action0 Action1 Action2 ... ActionN * EXCEPTION ORG DC.L DC.L DC.L

#N,I
EXCEPTION I,D0 #4,D0 Table,A0 (A0,D0),A0 (A0),A0 (A0) <address> <address0> <address1> <address2>

Test for I out of range IF I>N THEN exception Pick up value of I in D0 Each address is a longword A0 points to table of addresses A0 now points to case 1 in table A0 contains address of case 1 handler Execute case 1 handler Here is Address Address Address the table of case 0 of case 1 of case 2 of exceptions handler handler handler

NDC.L
...

<addressN>

Address of case N handler

Exception handler here

Addressing modes
Addressing modes are concerned with how an operand is located by the CPU. A computers addressing modes are almost entirely analogous to human addressing modes, as the following example demonstrate:
Heres 100 USD (literal value) Get the cash from 12 North Street (absolute address) Go to 10 East Street and they will tell you where to get the cash (indirect address) Go to 2 North Street and get the cash from the fifth house to the right (relative address)

Addressing modes
These four addressing modes show that we can provide data itself (i.e. the $100 cash), say exactly where it is, or explain how you go about finding where it is Up to now we have dealt largely with the absolute addressing mode, in which the actual address in memory of an operand is specified by the instruction, or with register direct addressing in which the address of an operand is a register

Addressing modes
We now introduce other ways of specifying the location of an operand. Because the address of an operand can be calculated in several ways, we use the term effective address as a general expression for the address of an operand

Addressing modes: absolute addressing

In absolute or direct addressing the operand field of the instruction provides the address of the operand in memory E.g., the instruction MOVE 1234,D0 copies the contents of memory location 1234 into data register D0:
MOVE D0,1234 MOVE 1234,1234 ADD 1234,D0 SUB TEMP,D2 [D0] -> [1234] [1234]->[1234] [D0]<-[D0]+[1234] [D2]<-[D2]-[Temp]

Remember that [1234] is a shorthand for [M(1234)] and means the contents of memory location 1234

Addressing modes: absolute addressing

High Level Low Level Language Language x:=y Machine Code Memory Map 11FB 1000 1001 Opcode Operand Operand MOVE y,x 11FB10001001 400 ... 402 ... 404 ORG $1000 DS.B 1 DS.B 1

y x

1000 1001

x y

Data Data

Addressing modes: immediate addressing

Immediate addressing is also referred to as literal addressing. Immediate addressing is provided by all microprocessors and allow the programmer to specify a constant as an operand The value following the op-code in an instruction is not a reference to the address of an operand but is the actual operand itself. In 68K assembly language, the symbol # precedes the operand to indicate immediate addressing

Addressing modes: immediate addressing

1.MOVE 1234,D0 2.MOVE #1234,D0 3.ADD 1234,D0 4.ADD #1234,D0

Addressing modes: immediate addressing

Dont confuse the symbol # with the symbols $ (hexadecimal) or % (binary). Expressions MOVE #25,D0 MOVE #$19,D0 MOVE #%00011001,D0 have identical effects

Addressing modes: application of immediate addressing

Immediate addressing is used whenever the value of the operand required by an instruction is known at the time the program is written That is, it is used to handle constants as opposed to variables. Immediate addressing is faster than absolute addressing, because only one memory reference is required to read the instruction during the fetch phase E.g., when the instruction MOVE #5,D0 is read from memory in a fetch cycle, the operand, 5, is available immediately without a further memory access to location 5 to read the actual operand

Addressing modes: application of immediate addressing as an arithmetic constant

MOVE NUM,D0 [D0]<-[M(NUM)] ADD #22,D0 [D0]<-[D0]+22 MOVE D0,NUM [M(NUM)]<-[D0] This sequence of instructions is equivalent to the high-level language construct NUM:=NUM+22 and increases the value in memory location NUM by 22.

Addressing modes: application of immediate addressing as an arithmetic constant

The 68K can, in fact, add an immediate operand to a memory location directly without using a data register by means of the special add immediate instruction ADDI. For example, ADDI #22,NUM adds the constant value 22 to the contents of the location called NUM.

Addressing modes: application of immediate addressing in a comparison with a constant

Consider the test on a variable NUM to determine whether it lies in the range 7<NUM<25 MOVE NUM,D0 Get NUM in D0 CMP #8,D0 Compare it with 8 BMI FALSE IF negative NUM<=7 CMP #25,D0 Compare it with 25 BPL FALSE IF positive NUM>24 TRUE ... ... FALSE ...

Addressing modes: application of immediate addressing as a method of terminating loop structures

A typical loop structure is illustrated in BASIC, Pascal and C:

10 IF FOR I=1 TO N ... 50 NEXT I FOR I:=1 TO N DO BEGIN ... END for (int i:=0; i<N+1; i++) { ... }

The higher level language FOR... construct can readily by translated into 68K assembly language.

Addressing modes: application of immediate addressing as a method of terminating loop structures

EQU 10 ... MOVE #1,D0 NEXT ... ... ... ... ADD #1,D0 #N+1,D0 BNE NEXT

Define the loop size weve used N=10 here Load D0 with initial value of the loop counter

Start of the loop

Body of loop
Increment the loop counter CMP Test for the end of the loop IF not end THEN repeat loop

Addressing modes: application of immediate addressing as a method of terminating loop structures

At the end of the loop, the counter is incremented by means of the instruction ADD #1,D0. The counter D0 is then compared with its terminal value by CMP #N+1,D0 On the last time round the loop, the variable I becomes N+1 after incrementing and the branch to NEXT is not taken, allowing the loop to be exited

Address register indirect addressing

At the end of the loop, the counter is incremented by means of the instruction ADD #1,D0. The counter D0 is then compared with its terminal value by CMP #N+1,D0 On the last time round the loop, the variable I becomes N+1 after incrementing and the branch to NEXT is not taken, allowing the loop to be exited