THERMAL RESISTANCE VBE / VDS TESTER

MODEL 9424-KTB/L 9425-PUB

James A. Ochea TF2 Equipment Technician I

www.fairchildsemi.com

04 Jul 2008 July 2008 P Hipe

PRESENTATION OUTLINE

INTRODUCTION OPERATION PANEL DV240-PU FRONT & REAT PANEL FUNDAMENTAL MEASUREMENT CIRCUIT VBE / VDS TIMING DIAGRAM FLOW CHART RESOURCE BOARDS ASSIGNMENT CONTACT CHECK DETECTION
VBE1 VBE VBE2

+
-

S 300

IM

-5V IDS

POWER TIME

INTRODUCTION

Overview DV240 is an automatic test system designed to evaluate a full range of discrete devices from small signal to high power transistors (NPN/PNP), Darlingtons, and MOSFETs (N-channel/P-channel). The system operates by forcing a power pulse to the device and then displays a digital readout of the variation of base to emitter voltage VBE or VDS in the case of FET before and after the pulse was applied. DV240 can be used for both manual testing and automatic testing using handlers. A real time parallel testing of both DC parameters and thermal impedance can achieved by coupling with TESEC DC testers, where high level programming of limits and binning information can be accomplished through the larger systems computer.

Besides thermal resistance applications, such as evaluating die attachment, the tester can be used to obtain data for determining safe operating area. A device protection circuit is built-in to cut-off power when avalanche occurs.

INTRODUCTION

Features
- Fast and accurate VBE / VDS measurement. - Display of both VBE1 / VDS1 and VBE or VDS is achieved. - A special contact check function prevents the wrong measurement and mis-binning due to contact failure. - Oscillation detection function prevents the wrong measurement and mis-binning due to oscillations - Digitalized operation & high speed data logging. - Tester can be controlled externally through IEEE-488 I/F - Interfaces with the DC testers and handlers. - Standardized to 19 inch cabinet rack.

INTRODUCTION
Specifications Measurement range Polarity : Pretest : Measurement range :

PNP/NPN, P-MOSFET/N-MOSFET Contact check, B-E open and short tests VBE1 or VDS1 0000~4095 mV VBE or VDS 0000~1999 mV (measurement accurate to 2% or 3 mV whichever is greater)
Range 00.01~39.99A 01~99 mA 01.0~19.9V (Fix value of 12V is also possible) 100 s~9.99 s 010~999 s 0000~1999 mV 001~199 V Step 10mA 1mA 0.1V Accuracy (1 + 2mA) 01~39mA ( 1.5 %) 40~99mA( 3 %) 5V Digit 4 2 2

Range of Settings
Item Forcing Current IE / IDS Sensing Current IM Gate Limit Voltage Gate-L Power Dissipation Time PT Delay Time DT Upper Limit / Lower Limit VCB / VDS

1s 1s 1mV 1V

(Crystal) 3s ( Crystal) Digital Comparison (0.02 % + 0.1V)

3 3 3 3

Forcing Power Range Diagram

39.99 30 8 6 IE / IDS (A) 4 3

VCB

20 100 / VDS (V)

199

Fundamental Measurement Circuit

VBE Test Circuit (NPN TR)
VBE1 POWER VBE2

VCB

VCB

VCB

VBE1

IM
-64V

I
E

VBE2

IM
-64V

-64V

VBE=VBE1-VBE2
NOTE: Device is turn ON before Power Time since IM is already present during 1st sampling (VBE1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.

Fundamental Measurement Circuit

VDS Test Circuit (N-MOS FET)
VDS1 POWER VDS2

VDS

VDS1
ON
250

VDS2 ON IM
250 250

IM

IM

-5V +64V

-5V

-5V IDS
+64V

+64V

VDS=VDS1-VDS2
NOTE: Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.

Fundamental Measurement Circuit

VGS Test Circuit (N-IGBT)
VGS1
VDS
+
250

POWER
VDS
+
-

VGS2
VDS
+ -

VGS1

250

250

VGS1

-5V IM ID

-5V IM

-5V IM

- 64V

- 64V

- 64V

NOTE:

VGS=VGS1-VGS2

Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.

Fundamental Measurement Circuit

VCE Test Circuit (N-IGBT)
VCE1
+15V
250

POWER
VCE
+

VCE2
+15V
250

+15V
250

VCE1

VCE2

IM
ID -64V - 64V

IM -64V

IM

NOTE:

VCE=VCE1-VCE2

Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.

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Fundamental Measurement Circuit

VF Test Circuit (N-DIODE)

VF1
C

POWER
C C

VF2

VF1
E

VF2
E E

IM
+64V

ID
+64V

IM
+64V

IM

NOTE:

VF=VF1-VF2

Gate voltage already have 5V during turn ON even without test. 5V for PNP and -5V for NPN. Device is turn ON before Power Time since IM is already present during 1st sampling (VDS1) and notice increase of voltage (see timing diagram) during PT since it is being heat up. After which, the voltage will drop after DT for 2nd sampling.

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VBE Test Timing (NPN TR/PNP TR)

VCB

VBE1 VBE

VBE2

POWER TIME

IM ON VCB ON IE ON DELAY TIME S/ 16ms 10us (fix)

POWER TIME

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VDS Test Timing

DRAIN

SOURCE VDS1 POWER TIME VDS2

DELAY TIME 0V

GATE

-5V

VDS ON IDS ON VGATE ON S/ 10us (fix) POWER TIME

13

VGS Test Timing (N-IGBT/P-IGBT)

VCB

POWER TIME

SOURCE VGS1 VGS2

IM ON

VCB ON POWER TIME

IE ON DELAY TIME S/ (SAMPLE HOLD) sample (10us fix)

14

VCE Test Timing (N-IGBT)

COLLECTOR

EMITTER VCE1 POWER TIME

VCE2

DELAY TIME

GATE -15V

VCE ON IC ON VG ON S/ (SAMPLE HOLD) 10us (fix) POWER TIME DT

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VF Test Timing (N-DIODE)

EMITTER VF1 VF2

DELAY TIME POWER TIME

IM ON

IE ON

POWER TIME

DT

S/ (SAMPLE HOLD) 10us (fix)

16

RESOURCE BOARDS ASSIGNMENT

PT9131 VCB control board PT9404 IM board PT9406 IC limit PT9117 IE GEN

PT9403 Resistor Board

CP8751B Controller Board CP8744 Resistor Board CP8742 VG Gen CP8745 IS Generator

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Flow Chart
Test Start Test Condition Load LEGEND: Reject Indicator Result Indicator

H-Up Check No Contact Check No VBE1 Read

Yes

Yes

CONTF
1

When an avalanche is detected, power forcing is cut-off at high speed and AVAL is displayed When VBE1 < VBE2, ERROR is displayed

VBE1 > 3V
No

Yes

OPEN

VBE1 < 0.2V No Power Forcing

Yes

SHORT
1

3&4

AVAL

The following sheet is default value when it is initially shipped from the vendor.

VBE Read

A B

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Flow Chart Continuation

A
Yes

B
OSCILLATION

Oscillation No Error No Upper Limit < VBE No

Yes

ERROR

Yes

HIGH

VBE < Lower Limit

No PASS END

Yes

LOW

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HANDLER Connectors
(pin arrangement)
HANDLER 57GE- 40140-751 (DDK) Pin No. Signal PASS-L FAIL-L RETURN (+12V) START-L END-L Pin No. 8 9 10 11 12 13 14 Signal GND SHIELD +12V -KT

HANDLER 1
-L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

1 2 3 4 5 6 7 HANDLER 57GE- 40140-751 (DDK)

Pin No. 1 2

Signal PASS-L LOW-L

Pin No. 8 9

Signal GND

HANDLER 2
-L indicates a low true.

3
4 5 6 7

HIGH-L
REJECT-L RETURN (+12V) START-L END-L

10
11 12 13 14

SHIELD
+12V -KT

Nos. 13 & 14 are not provided for SD-1612A

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HANDLER Connectors
(pin arrangement)
HANDLER 57GE- 40140-751 (DDK) Pin No. Signal PASS-L LOW-L HIGH-L REJECT-L RETURN (+12V) START-L END-L Pin No. 8 9 10 11 12 13 14 Signal CONTF-L GND SHIELD +12V -KT

HANDLER 3
(For the tester of P-ROM version -02.C or later) -L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

1 2 3 4 5 6 7 HANDLER 57GE- 40140-751 (DDK)

Pin No. 1 2

Signal PASS-L OPEN-L

Pin No. 8 9

Signal GND

HANDLER 4
(For the tester of P-ROM version -01.J or later) -L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

3
4 5 6 7

REJECT-L
HIGH-L or LOW-L RETURN (+12V) START-L END-L

10
11 12 13 14

SHIELD
+12V -KT

21

HANDLER Connectors
(pin arrangement)
HANDLER 57GE- 40140-751 (DDK) Pin No. Signal PASS-L OPEN-L SHORT-L REJECT-L RETURN (+12V) START-L END-L Pin No. 8 9 10 11 12 13 14 Signal CONTF-L GND SHIELD +12V -KT

HANDLER 5
(For the tester of P-ROM version -02.D or later) -L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

1 2 3 4 5 6 7 HANDLER 57GE- 40140-751 (DDK)

Pin No. 1 2

Signal PASS-L OPEN-L/SHORT-L

Pin No. 8 9

Signal GND

HANDLER 6
(For the tester of P-ROM version -02.E or later) -L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

3
4 5 6 7

REJECT-L
HIGH-L or LOW-L RETURN (+12V) START-L END-L

10
11 12 13 14

SHIELD
+12V -KT

22

HANDLER Connectors
(pin arrangement)
HANDLER 57GE- 40140-751 (DDK) Pin No. Signal PASS-L OPEN-L/SHORT-L REJECT-L HIGH/LOW-L RETURN (+12V) START-L END-L Pin No. 8 9 10 11 12 13 14 Signal GND SHIELD +12V -KT

HANDLER 7
(For the tester of P-ROM version -02.F or later) -L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

1 2 3 4 5 6 7 HANDLER 57GE- 40140-751 (DDK)

Pin No. 1 2

Signal PASS-L CONTF-L/OSC-L

Pin No. 8 9

Signal GND

HANDLER 8
(For the tester of P-ROM version -02.U or later) -L indicates a low true. Nos. 13 & 14 are not provided for SD-1612A

3
4 5 6 7

OPEN-L/SHORT-L
REJECT-L RETURN (+12V) START-L END-L

10
11 12 13 14

SHIELD
+12V -KT

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HANDLER Connectors
(pin arrangement)
HANDLER 57GE- 40140-751 (DDK)

Pin No.
1 2 3 4 5 6 7

Signal
PASS-L OPEN-L/AVAL1-L SHORT-L/AVAL2-L REJECT-L RETURN (+12V) START-L END-L

Pin No.
8 9 10 11 12 13 14

Signal
CONTF-L GND SHIELD +12V -KT

HANDLER 9
(For the tester of P-ROM version -03.O or later) -L indicates a low true. AVAL1 indicates AVAL (GATE LIMIT) Nos. 13 & 14 are not provided for SD-1612A AVAL2 indicates AVAL (0.2V detect, IC Limit)

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USER (for the 9424-KT/L tester)

HANDLER 57GE- 40140-751 (DDK) Pin No. 1 2 3 4 5 6 7 Signal BIN1-L BIN2-L BIN3-L BIN4-L RETURN (+12V) START-L END-L Pin No. 8 9 10 11 12 13 14 Signal BIN5-L GND SHIELD +12V -KT

-L indicates a low true.

25

Test Start Signal Low true is set at time of shipment Switching to high true can be made by the DIP switch SW-4 to SW-6 Required signal pulse is 1ms Test End Signal Low true is set at time of shipment Switching to high true can be made by the DIP switch SW-2 Required signal pulse is 3ms Bin Signals Low true is set at time of shipment Switching to high true can be made by the DIP switch SW-1 Output signal is HOLD

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2-bin mode (HAND1) PASS, FAIL (LOW, HIGH, REJECT) 4-bin mode (HAND2) PASS, LOW, HIGH, REJECT (AVAL, ERROR, OSC, OPEN, SHORT, CONTF) 5-bin mode (HAND3) PASS, LOW, HIGH, CONTF, REJECT (AVAL, ERROR, OSC, OPEN, SHORT) 4-bin mode (HAND4) PASS, OPEN, HIGH/LOW, REJECT (AVAL, ERROR, OSC, SHORT, CONTF) 5-bin mode (HAND5) PASS, OPEN, SHORT, CONTF, REJECT (HIGH, LOW, AVAL, ERROR, OSC) 4-bin mode (HAND6) PASS, OPEN/SHORT, HIGH/LOW, REJECT (AVAL, ERROR, OSC, CONTF) 4-bin mode (HAND7) PASS, OPEN/SHORT, REJECT, HIGH/LOW (AVAL, ERROR, OSC, CONTF) 4-bin mode (HAND8) PASS, CONTF/OSC, OPEN/SHORT, REJECT (AVAL, ERROR, HIGH, LOW) 5-bin mode (HAND9) PASS, OPEN/AVAL1(GATE LIMIT), SHORT/AVAL2 (0.2V detect, IC limit), REJECT (LOW, HIGH, OSC, ERROR, VCB ALARM, CONTF)

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SIGNAL CIRCUITS

PC817

SW4-3 5 SW4-5 RETURN

360

SW4-4 6 START

SW4-6

12V

INTPUT CIRCUIT (START SIGNAL)

2K LS06 OUTPUT

OUTPUT CIRCUIT

(END, BIN SIGNALS)

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DIP SWITCH SETTING

Logic setting (high true & low true) is made by the DIP switch SW4 on the rear panel of the main unit (KT). NOTICE: (a.) SORT=PASS, HIGH/FAIL, LOW, REJECT (b.) When the switches, No.3 and No.4 are turned ON, the switches No.5 and No.6 must be turned OFF. (c.) When the switches, No.5 and No.6 are turned ON, the switches No.3 and No.4 must be turned OFF. (d.) The SW4 switch is set to conform to the interface specifications at the time of shipment. (e.) -H indicates high true and -L indicates low true.

29

EXT Connector (Pin Arrangement)

NOTICE: (a.) The *1 mark indicates that the pin is not in use. (b.) -H indicates high true and -L indicates low true.

TEST start Signal (AUXX,AUXY, or AUXZ) Always low true Required signal pulse is 1ms Select 1 signal among AUXX,AUXY and AUXZ with DIP switch SW3. One desired switch only must be turned ON and 2 other switches must be turned OFF

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CHECK TERMINAL Site

1 5 6 7

CHECK TERMINAL CYCLE S/H1 DELAY S/H2

VCB ON VG ON IE ON

GND

The following check terminals are provided, which are to be checked by an oscilloscope (0 to +3.4V, low true (1.) CYCLE (2.) VCB ON (3.) VG ON (4.) IE ON (5.) S/H1 (6.) DELAY (7.) S/H2 (8.) GND Low level from the start to the end of a test Low level while the VCB power is ON. Low level while the gate power is ON in FET measurement Low level while the IE power is ON Low level during the 1st sampling Low level during the delay time Low level during the 2nd sampling The ground terminal for an oscilloscope

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OPERATION PREREQUISITES
1 OFF 6 1 OFF

1 OFF

OFF

SW1

SW2

SW3

SW4

SW1 >> sets the baud rates of the SERIAL connector

SW3 >> sets the start signal type of the EXT connector

SW4 >> sets the logic (high true and low true) for signal of the HANDLER connector
SW2 >> sets the address of the GPIIB connector

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Contact Check Detection

Contact Check of Transistors (a) (b) Connect the force (F) and sense (S) terminals for each of B, C and E. Set the POLARITY Switch to NPN. Turn ON the Contact Check Switch. (c) (d) Push the START Switches. If there is no CONTACT FAIL, it is OK Remove the shorting wire connected to BASE and push the START Switches.

If there is CONTACT FAIL, it is OK.

(e) Return to (a) condition. Remove the shorting wire connected to COLLECTOR and push the START Switches. If there is CONTACT FAIL, it is OK. (f) Return to (a) condition. Remove the shorting wire connected to EMITTER and push the START Switches. If there is CONTACT FAIL, it is OK. (g) Return to (a) condition, set the POLARITY switch to PNP. Conduct steps (c) to (f) to confirm that PNP is OK. (h) If under any condition, there is no CONTACT FAIL, the system is OK.

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Contact Check Detection

Contact Check of FET (a) (b) Connect the force (F) and sense (S) terminals for Drain and Source. Set the POLARITY Switch to N-MOS FET. Turn ON the Contact Check Switch. (c) (d) Push the START Switches. If there is no CONTACT FAIL, it is OK Remove the shorting wire connected to DRAIN and push the START Switches. If there is CONTACT FAIL, it is OK. (e) Return to (a) condition. Remove the shorting wire connected to SOURCE and push the START Switches. If there is CONTACT FAIL, it is OK. (g) Return to (a) condition, set the POLARITY switch to P-MOS FET. Conduct steps (c) to (e) to confirm that P-MOS FET is OK. (h) If under any condition, there is no CONTACT FAIL, the system is OK.
NOTE: Contact resistance limit is adjustable from 50, 100, 150, 200 located at CP8741. It can be set for total contact resistance at G, D & S.

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