State Reduction and State Ass

ECE 331 Digital System Design
State Reduction and State Assignment

(Lecture #22)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
Material to be covered
Chapter 15: Sections 1 9
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ECE 331 - Digital System Design
Sequential Circuit Design

Understand specifications
Draw state graph (to describe state machine behavior) Construct state table (from state graph)
Perform state minimization (if necessary)

Encode states (aka. state assignment) Create state-assigned table
Select type of Flip-Flop to use

Determine Flip-Flop input equations and FSM output equation(s)
Draw logic diagram

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Elimination of Redundant States
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Elimination of Redundant States

In Unit 14, we were careful to avoid introducing unnecessary states when setting up a state graph or table. We will now approach the problem of deriving the state graph somewhat differently. When first setting up the state table, we will not be overly concerned with inclusion of extra states, and when the table is complete, we will eliminate any redundant states. We will rework Example 1 in Section 14.3 using excess states, and then eliminate the excess states.
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Example: Sequence Detector

A sequential circuit has one input (X) and one output (Z). The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. Find a Mealy state graph. A typical input and output sequence is:
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State Table
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Since states H and I have the same next states and the same outputs, there is no way of telling states H and I apart. We can replace I with H.
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Reduced State Table

Reduced State Graph

Determination of Equivalent States
a b iff d f and ch
a d iff a d and c e
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Implication Chart
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Implication Chart
After first pass.
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Implication Chart
After second pass.
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Implication Table Method

3. Go through the table square-by-square. If square i-j contains the implied pair m-n, and square m-n contains an X, then i j, and an X should be placed in square i-j. 4. If any Xs were added in step 3, repeat step 3 until no more Xs are added. 5. For each square i-j which does not contain an X, i j.
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Future site of another example.
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Derivation of FF Input Equations
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Derivation of FF Input Equations

After the number of states in a state table has been reduced, the following procedure can be used to derive the flip-flop input equations: 1. Assign flip-flop state values to correspond to the states in the reduced table. 2. Construct a transition table which gives the next states of the flip-flops as a function of the present states and inputs. 3. Derive the next-state maps from the transition table. 4. Find flip-flop input maps from the next-state maps using the techniques developed in Unit 12 and find the flip-flop input equations from the maps.
Example #1: FF Input Equations

1. Assign flip-flop state values to correspond to the states in the reduced table. 2. Construct a transition table which gives the next states of the flip-flops as a function of the present states and inputs.
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3. Derive the next-state maps from the transition table.
D FF Characteristic Equation:
Q+ = D
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4. Derive the flip-flop input maps from the next-state maps; determine the flip-flop input equations from the FF input maps.
JK Excitation Table
Q 0 0 1 1 Q+ 0 1 0 1 J 0 1 x x K x x 1 0
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1. Assign flip-flop state values to correspond to the states in the reduced table. 2. Construct a transition table which gives the next states of the flip-flops as a function of the present states and inputs.
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3. Derive the next-state maps from the transition table.
D FF Characteristic Equation:
Q+ = D
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4. Derive the flip-flop input maps from the next-state maps; determine the flip-flop input equations from the FF input maps.
SR Excitation Table
Q 0 0 1 1 Q+ 0 1 0 1 S 0 1 0 x R x 0 1 0
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State Assignment
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State Assignments
After the number of states in a state table has been reduced, the next step in realizing the transition table (aka. stateassigned table) is to assign flip-flop states (i.e. binary values) to correspond to the states in the state table. The cost of the logic required to realize a sequential circuit is strongly dependent on the way this state assignment is made.
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State Assignments
Given a sequential circuit with three states and two flip-flops (A and B), there are 4 3 2 = 24 possible state assignments for the three states.
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State Assignments
When realizing a three-state sequential circuit with symmetrical flip-flops (i.e. JK or SR), it is only necessary to try three different states to be assured of a minimum cost realization. Similarly, only three different assignments must be tried for four states.
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State Assignments
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Guidelines for State Assignment

Trying all nonequivalent state assignments is not practical in most cases. The following guidelines are useful in making assignments which will place 1s (or 0's) together in the next-state maps: 1. States which have the same next state for a given input should be given adjacent assignments. 2. States which are the next states of the same state should be given adjacent assignments. 3. States which have the same output for a given input should be given adjacent assignments.
Example: Selecting an Assignment
1. States which have the same next state for a given input should be given adjacent assignments. 2. States which are the next states of the same state should be given adjacent assignments. 3. States which have the same output for a given input should be given adjacent assignments.

Based on the State Assignment Guidelines: 1. (b, d) (c, f) (b, e) 2. (a, c) (d, f) (b, d) (b, f) (c, e) 3. (a, c) (b, d) (e, f)
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Resulting Transition Table:
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Derivation of FF input equations from next-state maps:
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One-Hot State Assignment

Sometimes reducing the number of flip-flops used is not as important as reducing the logic feeding into the flip-flops. Using a one-hot state assignment may help accomplish this. The one-hot assignment uses one flip-flop for each state, so a state machine with N states requires N flip-flops. Exactly one of the flip-flops is set to one in each state.
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Example: State Assignments

For a four-state FSM, three possible state assignments are:
State S0 Binary 00 Gray-code 00 One-hot 0001
S1
S2 S3 # of FF
01
10 11 2
01
11 10 2
0010
0100 1000 4
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State Reduction and State Ass

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ECE 331 Digital System Design

State Reduction and State Assignment

Chapter 15: Sections 1 9

ECE 331 - Digital System Design

Sequential Circuit Design

Perform state minimization (if necessary)

Select type of Flip-Flop to use

Draw logic diagram

Elimination of Redundant States

ECE 331 - Digital System Design

Elimination of Redundant States

ECE 331 - Digital System Design

Example: Sequence Detector

ECE 331 - Digital System Design

Example: Sequence Detector

Example: Sequence Detector

ECE 331 - Digital System Design

Example: Sequence Detector

Reduced State Table

Example: Sequence Detector

Reduced State Graph

Determination of Equivalent States

ECE 331 - Digital System Design

ECE 331 - Digital System Design

After first pass.

ECE 331 - Digital System Design

After second pass.

ECE 331 - Digital System Design

Implication Table Method

ECE 331 - Digital System Design

Future site of another example.

ECE 331 - Digital System Design

Derivation of FF Input Equations

ECE 331 - Digital System Design

Derivation of FF Input Equations

Example #1: FF Input Equations

ECE 331 - Digital System Design

Example #1: FF Input Equations

ECE 331 - Digital System Design

Example #1: FF Input Equations

Example #2: FF Input Equations

ECE 331 - Digital System Design

Example #2: FF Input Equations

Example #2: FF Input Equations

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

Guidelines for State Assignment

Example: Selecting an Assignment

Example: Selecting an Assignment

ECE 331 - Digital System Design

Example: Selecting an Assignment

ECE 331 - Digital System Design

Example: Selecting an Assignment

ECE 331 - Digital System Design

One-Hot State Assignment

ECE 331 - Digital System Design

Example: State Assignments

ECE 331 - Digital System Design

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