Gheorghe M.

tefan
http://arh.pub.ro/gstefan/

- 2014 -

Sequential circuits
Sequencing involves memorizing: to catch an event Memorizing request discrete time control through clock signal Our target: to learn how logic circuits can be used to memorize
Sequential circuits Elementary latches (no clock control) Clocked latches (transparent on the active level of clock) Master-Slave flip-flops (triggered by the active edge of clock) Register Applications Shift register Counter
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Elementary latches
reset-only latch

set-only latch

set-reset heterogeneous latch

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Digital Integrated Circuits - week two

Symmetric elementary latches

De Morgan laws: a+b = (ab) ab = (a+b)

The first latch problem: when? and how? on the same inputs The second latch problem: S= R = 0 or S = R = 1 trigger unpredictable switches
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Application: de-bouncing circuit

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Digital Integrated Circuits - week two

Elementary clocked latch

Partial decoupling of how? by when?
The circuit is transparent on the active level of clock

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Digital Integrated Circuits - week two

Data latch
Second latch problem is avoided (not solved) by adding

restriction: R = S Data latch remains transparent on the active level of clock The output follows the input, unless the level active clock is controlled

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Digital Integrated Circuits - week two

An improved version of data latch

Q = = = = = ((D CK) ((D CK) ((D CK) ((D CK) D CK + C (C (C (C (C D + (D CK))) (D + CK))) D + C CK)) D) (C CK)) C CK = D CK + C CK

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Digital Integrated Circuits - week two

The master-slave principle

How? and When? are finally separated A flip-flop, F-F, is a non-transparent structure if date is stable at the moment of the active edge of clock What the moment is?
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The moment
moment = tsu + t+ + th

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Digital Integrated Circuits - week two

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Delay F-F (DF-F)

The output follows the input synchronized with the active edge of clock The input D is delayed one clock cycle

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Digital Integrated Circuits - week two

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Register

#2: only for simulation purpose

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Registers are used for: storing buffering synchronizing delaying looping

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Shift register
00: nop: no operation, a mandatory function 01: load: initialize the registers state 10: leftShift: left shift with one position 11: rightShift: right shift with one position (logic or arithmetic)

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Counter

If (init) ... else ...

out <= out + 1;

suggests a multiplexer requests an increment circuit

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Digital Integrated Circuits - week two

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The structure of Digital Pixel Corrector

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Home work 2
Problems: 2.17, 2.24, 2.28

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Digital Integrated Circuits - week two

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