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CMOS inverter switch model CMOS inverter properties CMOS inverter loads line CMOS inverter voltage transfer characteristic The switch model of dynamic behavior of static CMOS inverter
CMOS INVERTER
Slide 2
VDD
VDD 2l
PMOS
PMOS In Out
In
Contacts
Out Metal 1
NMOS
Polysilicon
Two Inverters
Share power and ground Abut cells
VDD
Connect in Metal
Slide 4
Switch In Series
INPUT
Truth Table S1
S1 OFF OFF
S2 OFF ON OFF ON
PATH?
S2
ON ON
OUTPUT
Slide 5
Switch In Series
INPUT
S1 OFF OFF
S2 OFF ON
PATH? NO NO
S2
ON ON
OUTPUT
OFF ON
What Function ??
NO YES
Slide 6
S1 0
S2 0
PATH? 0
S2
OUTPUT
Circuits and Layout
Function = ??
CMOS VLSI Design Slide 7
Switch In Series
INPUT Truth Table (OFF/ON=0/1)
S1
S1 0 0
S2 0 1
PATH? 0 0
S2
OUTPUT
Circuits and Layout
Function = ??
CMOS VLSI Design Slide 8
Switch In Series
INPUT Truth Table (OFF/ON=0/1) S1
S1 0 0
S2 0 1 0
PATH? 0 0 0
S2
OUTPUT
Circuits and Layout
Function = ??
CMOS VLSI Design Slide 9
Switch In Series
INPUT Truth Table (OFF/ON=0/1) S1
S1 0 0
S2 0 1 0 1
PATH? 0 0 0 1
S2
1 1
OUTPUT
Switch In Parallel
INPUT
Truth Table
S1 OFF
S1 S2
S2 OFF ON
OFF ON
PATH? NO YES
YES YES
OFF
ON ON
OUTPUT
Circuits and Layout CMOS VLSI Design Slide 11
Switch In Parallel
INPUT Truth Table
S1 0
S1 S2
S2 0
PATH? 0
OUTPUT
Circuits and Layout
Function =??
CMOS VLSI Design Slide 12
Switch In Parallel
INPUT Truth Table
S1 0
S1 S2
S2 0 1
PATH? 0 1
OUTPUT
Circuits and Layout
Function =??
CMOS VLSI Design Slide 13
Switch In Parallel
INPUT Truth Table
S1 0
S1 S2
S2 0 1 0
PATH? 0 1 1
0 1
OUTPUT
Circuits and Layout
Function =??
CMOS VLSI Design Slide 14
Switch In Parallel
INPUT Truth Table
S1 0
S1 S2
S2 0 1 0
PATH? 0 1 1
0 1
1
OUTPUT
Circuits and Layout
1
Function = Logic OR
Slide 15
CMOS TRANSISTOR
Source Gate Drain pMOS
Complementary MOS P-channel MOS (pMOS) N-channel MOS (nMOS) pMOS P-type source and drain diffusions N substrate Mobility by holes nMOS N-type source and drain diffusions P substrate Mobility by electrons
CMOS VLSI Design Slide 16
Gate 0 1
Drain Gate
Gate 0
Source
nMOS
High Impedance
When a path exists
Impedance is low to allow ample flow of current
Source Closed
Gate=1
Drain
<< 10K
When no path
Impedance is high allowing almost no current flow between two terminals
Circuits and Layout
>> 100M
Drain
Slide 18
Gate
| VGS | < | VT |
Circuits and Layout
| VGS | > | VT |
CMOS VLSI Design Slide 19
Gate
Rp
Vout Rn
Vout
Vin 5 VDD
Circuits and Layout
Vin 5 0
CMOS VLSI Design Slide 21
VDD
Rp Vout CL Rn
Vout
CL
Vin 5 0
Circuits and Layout
Vin 5 VDD
CMOS VLSI Design
(a) Low-to-high
(b) High-to-low
Slide 22
SYMBOL
INPUT A = LOGIC 1
1. 2.
TRUTH TABLE
INPUT A = LOGIC 0
1. 2.
3.
NMOS is ON, PMOS is OFF. NMOS will transfer logic 0 (GND) to the output. Output Y = Logic 0
3.
PMOS is ON, NMOS is OFF. PMOS will transfer logic 1 (VDD) to the output. Output Y = Logic 1
Slide 23
3. In steady state, there always exists a path with finite resistance between the output and either VDD or GND. Typical values of the output resistance are in kW range.
4. The input resistance of the CMOS inverter is extremely high, as the gate of an MOS transistor is a virtually perfect insulator and draws no dc input current
Circuits and Layout CMOS VLSI Design Slide 24
Slide 25
Slide 26
Slide 27
The load-line curves of the PMOS device are obtained by a mirroring around the xaxis and a horizontal shift over VDD. This procedure is outlined in Figure below, where the subsequent steps to adjust the original PMOS I-V curves to the common coordinate set Vin, Vout and IDn are illustrated.
Slide 28
V DSp
Vout
Vout = V DD-VDSp
Transforming PMOS I-V characteristic to a common coordinate set (assuming VDD = 2.5 V).
CMOS VLSI Design Slide 29
DC transfer characteristics
Slide 30
PMOS
Vin = 0.5
Vin = 2
NMOS
Vout Figure 2: Load curves for NMOS and PMOS transistors of the static CMOS inverter ( VDD = 2.5 V). The dots represent the dc operation points for various input voltages
Circuits and Layout CMOS VLSI Design Slide 31
Slide 32
VDD
NMOS sat PMOS res
A
Vout (V)
1.5 1 0.5 0 0 0.5
B C
NMOS sat PMOS sat
Vout CL
2.5
Slide 33
Slide 34