Prepared by

SHIHABUDEEN H
8086 includes few features, which enhance
multiprocessing capability (it can be used with math
coprocessors like 8087, I/O processor 8089 etc.
Operates on +5v supply and single phase (single line)
clock frequency.(Clock is generated by separate
peripheral chip 8284).
8086 comes with different versions. 8086 runs at 5
MHz, 8086-2 runs at 8 MHz, 8086-1 runs at 10 MHz
It comes in 40-pin configuration with HMOS
technology having around 20,000 transistors in its
circuitry.
It has multiplexed address and data bus like 8085 due
to which the pin count is reduced considerably

Some of the pins serve particular function in
minimum mode(single processor mode) and
others function in maximum
mode(multiprocessor mode)
Control signals are mainly 3 groups

1. signals having common functions in
minimum mode and maximum mode
2. signals having special functions in minimum mode
3. signals having special functions in maximum mode


AD
15
AD
0
:-these are time multiplexed
address/data bus

A
19
A
16
/S
6
-S
3
these are time multiplexed
address/status lines.

S
6
is always low.

S
5

denotes the status of interrupt enable flag.
S
4
& S
3
denotes which segment register is used
for memory access. Address bits are separated
from status bits by ALE signal


S
4
S
3
segment
0 0 Data/Extra
0 1 Stack
1 0 Code/None
1 1 Data
7

:- Bus high enable signal indicate the

transfer of data over higher order data bus
:- when low it indicates the peripherals that
the processor is performing a memory or I/O
read operation
READY:- is an acknowledgement from
peripherals that they have completed the data
transfer
INTR :-interrupt request from peripherals . if a
request is pending ,the processor enters
interrupt acknowledgement cycle
:- the input is examined by aWAIT
instruction .when it is low , the execution will
continue , but the processor remains in an idle
state
NMI:- Non Maskable Interrupt . This is an edge
triggered interrupt and cannot be masked
using software
RESET:- the processor terminates its activity &
the execution start from FFFF0H

CLK: - clock input for the system timing
VCC:- + 5V power supply
GND:- Ground for internal circuit
MN/:- the logic level at this pin decides
whether the processor has to operate either in
single or multiprocessor mode

M/: the state of this line indicates whether
the CPU is having a memory or I/O operation
:- a read strobe for interrupt
acknowledgement cycles . when it is low , the
processor has accepted the interrupt
/

:-Data Transmit /Receive :- it denotes the

direction of data flow through the transceivers
:- when low it indicates the peripherals that
the processor is performing a memory or I/O
write operation

ALE:- Address latch Enable . Denotes the
availability of valid address on multiplexed
bus
HOLD,HLDA:- Hold& hold acknowledge:-
when hold is high , another master is
requesting the bus access. After receiving
HOLD request , the processor issues hold
acknowledge signal on HLDA pin
:-Data enable. Indicates the availability of
valid data over address/data line


2

,
1
,
0

status lines.Reflects the types of

operation







: this O/P indicates the other system bus
master will be prevented from gaining the system
bus , while lock is low

Operation
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
QS
0
,QS
1
:- Queue status . Indicates the status of
prefetch queue






0

1

:-Request/Grant . These pins
are used in other local masters , to force the
processor to release the local bus at the end of
current bus cycle
QS
1
QS
0
Indication
0 0 No operation
0 1 First byte of Opcode
1 0 Queue is empty
1 1 Subsequent byte of Opcode
8086 processor has a 16-bit data bus multiplexed
with the 16 lower address lines

The processor loads on the address bus (AD
0
to
AD
7
, AD
8
to AD
15
and A
16
to A
19
) the address to be
used, and sets the ALE. Thus the address signals
A
0
to A
15
are latched on the 74LS373.

On the next clock the processor resets the ALE and
the AD
0
to AD
7
and AD
8
to AD
15
lines are used to
carry data (D
0
to D
7
and D
8
to D
15
). The
enables the buffers of the 74LS245, while the /

specifies the direction (read/write)


The 74LS373 and the 74LS245 are used to
demultiplex the AD
0
to AD
7
and AD
8
to AD
15

lines. They also provide the necessary buffering
for the A
0
to A
7
, A
8
to A
15
, D
0
to D
7
and D
8
to
D
15
lines.

The rest of the address lines (A
16
to A
19
) as well
as control lines (, , and M/) need to be
buffered using the 74LS244 octal buffer.

During the first clocking period (T
1
), the address is sent to the
address and address/data connections, and the ALE, /

and
M/ signals are also output
During T
2
the , are asserted, and data appear on the bus
In T
4
all bus signals are deactivated in preparation for the next bus
cycle, and the signal returns to logic 1.
ADDRESS/DATA
WR
During the first clocking period (T
1
), the address is sent to the address
and address/data connections, and the ALE, /

and M/ signals
are also output
During T
2
the , are asserted
In T
3
the READY signal is sampled and if low, T
3
becomes a wait state,
to allow time to the memory to access data
The bus is sampled at the end of T
3
Finally, the signal is deactivated


8086 support 1MB of external memory .this
memory space is organized as bytes of data
stored at consecutive addresses over the range
00000H to FFFFFH
8086 can access any two consecutive bytes as
word of data
Lower addressed data is taken as LSB byte and
Higher addressed data as MSB byte of word
D15-D8 D7-D0
CS CS
BHE
A0 A1---A19
UPPER BANK
LOWER BANK
ODD
EVEN
Memory is organized as even and odd banks , each of 512KB,
byte data with even address is transferred on D
7
to D
0
and
byte data with odd addresses transferred on D
15
to D
8
lines

Instruction stream is fetched from the memory
as words .then there are 3 possibilities
1: Both may be data
2: both the bytes may be Opcode
3: one of the byte may be Data while the other
maybe Opcode
All the 3 possibilities are taken care of by the
decoder circuit , which further derives the
signals those acts as input to the timing and
control unit
The timing and control unit derives all signals
required for the execution of instruction
7 0 memory address
FFFFFH
FFFFEH





00002H
00001H
00000H


8 bits
Memory address space
The locations from FFFF0H to FFFFF H are
reserved for operations including jump to
initialization programme and I/O processor
initialization
The locations 00000H to 003FFH are reserved
for interrupt vector table
8086 can address up to 64 KB I/O byte registers or
32 k word I/O registers
Address of an I/O device must not be greater than
16 bits, 2
16
=64 KB I/O devices can be accessed by
CPU

I/O address appear on address lines A0 to A15
A16 to A19 are at logic 0 level

during I/O
operations
DX register is user as 16 bit I/O address pointer.
I/O ports are addressed in the same manner as
memory locations


In a minimum mode 8086 system, the
microprocessor 8086 is operated in minimum
mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out
by the microprocessor chip itself. There is a
single microprocessor in the minimum mode
system. The remaining components in the
system are latches, transceivers, clock generator,
memory and I/O devices.
Some type of chip selection logic may be
required for selecting memory or I/O devices,
depending upon the address map of the system.

Latches are generally buffered output D-type
flip-flops like 74LS373 or 8282. They are used for
separating the valid address from the
multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
Transceivers are the bidirectional buffers and
some times they are called as data amplifiers.
They are required to separate the valid data
from the time multiplexed address/data signals.
CLK
READY
RESET
8284A
CLOCK
GENERATOR
WAIT STATE
GENERATOR
MN/
M/
INTA
RD
WR
DT/ R

DEN
ALE
BHE
AD0-AD15
A16-A19
8286
TRANCEIVER

RAM 2142
2716
PROM
PERIPHERAL
DATA
ADDR/DATA
ADDR
8282
LATCH
CONTROL
They are controlled by two signals namely, DEN
and DT/ R

.
The DT/ R

signal indicates the direction of data,

i.e. from or to the processor. The system contains
memory for the monitor and users program
storage.
Usually, EPROM are used for monitor storage,
while RAM for users program storage. A system
may contain I/O devices.

The clock generator generates the clock from the
crystal oscillator and then shapes it and divides
to make it more precise so that it can be used as
an accurate timing reference for the system.
The clock generator also synchronizes some
external signal with the system clock. It has 20
address lines and 16 data lines, the 8086 CPU
requires three octal address latches and two octal
data buffers for the complete address and data
separation.
The working of the minimum mode configuration
system can be better described in terms of the timing
diagrams rather than qualitatively describing the
operations.
The opcode fetch and read cycles are similar. Hence
the timing diagram can be categorized in two parts,
the first is the timing diagram for read cycle and the
second is the timing diagram for write cycle.
The read cycle begins in T
1
with the assertion of
address latch enable (ALE) signal and also
M/ signal. During the negative going edge of this
signal, the valid address is latched on the local bus.

The BHE and
0
signals address low, high or both
bytes. From T
1
to T
4
, the M/ signal indicates a
memory or I/O operation.
At T
2
, the address is removed from the local bus and
is sent to the output. The bus is then tristated. The
read (RD) control signal is also activated in T
2
.
The read (RD) signal causes the address device to
enable its data bus drivers. After RDgoes low, the
valid data is available on the data bus.
The addressed device will drive the READY line
high. When the processor returns the read signal to
high level, the addressed device will again tristate
its bus drivers.
A write cycle also begins with the assertion of ALE
and the emission of the address. The M/ signal
is again asserted to indicate a memory or I/O
operation. In T
2
, after sending the address in T
1
,
the processor sends the data to be written to the
addressed location.
The data remains on the bus until middle of
T
4
state. The becomes active at the beginning of
T
2
(unlike is somewhat delayed in T
2
to Provide
time for floating).
The and

0
signals are used to select the
proper byte or bytes of memory or I/O word to be
read or write.
M/



Transfer Type

0 0 1 I / O read
0 1 0 I/O write
1 0 1 Memory read
1 1 0 Memory write

Data transfer table
The M/ , and signals indicate the
type of data transfer as specified in table below
The HOLD pin is checked at leading edge of each
clock pulse. If it is received active by the processor
before T
4
of the previous cycle or during T
1
state of
the current cycle, the CPU activates HLDA in the
next clock cycle and for succeeding bus cycles, the
bus will be given to another requesting master.
The control of the bus is not regained by the
processor until the requesting master does not
drop the HOLD pin low. When the request is
dropped by the requesting master, the HLDA is
dropped by the processor at the trailing edge of
the next clock
In the maximum mode, the 8086 is operated by
strapping the MN/ pin to ground.
In this mode, the processor derives the status
signal
2

,
1
,
0

. Another chip called bus

controller derives the control signal using this
status information .
In the maximum mode, there may be more
than one microprocessor in the system
configuration.
The components in the system are same as in
the minimum mode system.
CLK
READY
RESET
8284A
CLOCK
GENERATOR
WAIT STATE
GENERATOR
MN/

AD0-AD15
A16-A19
DATA
BUFFERS

RAM 2142
2716
PROM
PERIPHERAL
DATA
ADDR/DATA
ADDR
8282
LATCH
8288
BUS
CONTROLER


CONTROL





/

CLK









The basic function of the bus controller chip
IC8288, is to derive control signals like RD and
WR ( for memory and I/O devices),
DT/R

, DEN,ALE etc. using the information by the

processor on the status lines.
The bus controller chip has input lines
2

,
1
,
0

and
CLK. These inputs to 8288 are driven by CPU.
It derives the outputs DT/ R

, DEN,ALE, ,
,, , . The
, and CEN pins are specially useful for
multiprocessor systems.
and are generally grounded. CEN
pin is usually tied to +5V. The significance of
the MCE/PDENoutput depends upon the
status of the pin.
If is grounded, it acts as master cascade
enable to control cascade 8259A, else it acts as
peripheral data enable used in the multiple bus
configurations.
pin used to issue two interrupt
acknowledge pulses to the interrupt controller
or to an interrupting device.
, are I/O read command and I/O
write command signals respectively . These signals
enable an I/O interface to read or write the data
from or to the address port.
The , are memory read command
and memory write command signals respectively
and may be used as memory read or write signals.
All these command signals instructs the memory
to accept or send data from or to the bus.
For both of these write command signals, the
advanced signals namely
are available.
They also serve the same purpose, but are
activated one clock cycle earlier than the
signals respectively.
The maximum mode system timing diagrams
are divided in two portions as read (input) and
write (output) timing diagrams.
The address/data and address/status timings
are similar to the minimum mode.
ALE is asserted in T
1
, just like minimum mode.
Here the only difference between in timing
diagram between minimum mode and
maximum mode is the status signals used and
the available control and advanced command
signals.

2

,
1
,
0

are set at the beginning of bus
cycle.8288 bus controller will output a pulse as
on the ALE and apply a required signal to its
DT/ R

pin during T
1
In T
2
, 8288 will set DEN=1 thus enabling
transceivers, and for an input it will activate
or . These signals are activated
until T
4
. For an output, the or
is activated from T
2
to T
4
and or
is activated from T
3
to T
4
. The status
bit S
0
to S
2
remains active until T
3
and become
passive during T
3
and T
4
.
If reader input is not activated before T
3
, wait
state will be inserted between T
3
and T
4

The request/grant response sequence contains
a series of three pulses. The request/grant pins
are checked at each rising pulse of clock input.
When a request is detected and if the condition
for HOLD request are satisfied, the processor
issues a grant pulse over the

pin
immediately during T
4
(current) or T
1
(next)
state.
When the requesting master receives this pulse,
it accepts the control of the bus, it sends a
release pulse to the processor using

pin
8088P

Both are 40 pin DIP
8086 is having 16 bit data bus and 20 bit
address bus
8088 is having 8 bit data bus and 20 bit address
bus
Pin no 34 is /S7 for 8086 but for 8088 it is

0
(status pin)
8086 :- 6 byte instruction prefetch queue
8088 :- 4 byte instruction prefetch queue

8086 :- M/ control signal
8088 :-

/IO control signal

8086 draws a maximum supply current of 360
mA , For 8088 it is 340 mA
Both requires +5v power supply
Temperature range 32
0
FH to 180
0
FH
Execution time is more in 8088 as compared to
8086



8088 can execute the complete instruction set of
8086
Address lines A
8
to A
15
are not multiplexed in
8088
In 8088 ,BIU will fetch a from memory if at
least one byte is free in the queue , but in 8086
at least 2 bytes should be free for next
instruction fetch