The End of EDA

Toward System Design

Ral Camposano
November, 2014

The End of EDA

What we may be witnessing is not just the
commoditization of electronics,
or the passing of a particular period of
electronic design / EDA,
but the end of electronic design / EDA as such:
that is, the end point of a technological evolution
and the universalization of the use of electronics
as the final form of intelligence in everything [1].
[1]

Paraphrasing Francis Fukuyamas essay "The End of History?" The National Interest, 1989

The Free Lunch is (largely) Over

2014
Fastest i7
3.6/4.0GHz, 150W
Fastest Xeon 3.4/3.7GHz, 155W

Intel CPU Introductions (graph updated August 2009; article text original from December 2004)
Source: The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software

Electronics $ 91
Other
$120
4

SW >$42 per Device

Systems Companies Capturing Value

Revenue
$B
200

150

Samsung
Apple
Microsoft
Amazon

100

Google
Intel
Facebook

50

0
2005

2006

2007

2008

2009

2010

2011

2012

2013

HW vs. SW

Big Switch Networks

Patterson / Hennessy The HW / SW Interface

Software-Defined Satellite

Wikipedia

Xilinx

EDA also Evolved into (mostly) SW

Gen 1 1960-1980
CALMA, Computervision, Applicon, Zuken
Customized Workstation + Artwork Editing SW

DMV 1981-1988
Daisy, Mentor, Valid
Still substantial focus on Hardware sales

Gen 3 1988
Cadence (88 ECAD +SDA), Mentor, Synopsys (Optimal
Solutions 86)
Software
8

EDA
$B
$8

$7

CDNS goes ratable

$6

SNPS goes ratable

$5

$4

$3

$2

$1

EDAC MSS
$1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

EDA
$B
$8

CAGR = 6%
$7

CDNS goes ratable

$6

SNPS goes ratable

$5

$4

$3

$2

$1

EDAC MSS
$1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

10

Buffets Valuation Indicator

1950

1960

1970

1980

1990

2000

2010

Source: Board of Governors of the Federal Reserve System and U.S. Bureau of Economic Analysis

11

Gross World Product

$T
$80

$70

$60

$50

$40

$30

$20

$10

$-

Source: World Bank

12

Gross World Product

$T
$80

$70

CAGR = 6.1%
$60

$50

$40

$30

$20

$10

$-

Source: World Bank

13

Semiconductors
$T

$B

$80

$400

$70

$350

$60

$300

$50

$250

$40

$200

$30

$150

$20

$100

$10

$50

$-

$-

Source: SIA

14

Semi / WDC
0.7%

0.6%

0.5%

0.4%

0.3%

0.2%

0.1%

0.0%

15

Semi / WDC
0.7%

0.6%

0.5%

0.4%

0.45%

0.3%

0.2%

0.1%

0.0%

16

EDA
$B
$8

$400

$7

$350

$6

$300

$5

$250

$4

$200

$3

$150

$2

$100

$1

$50

$-

$-

Source: EDAC

17

EDA
$B

$B

$8

$400

$7

$350

$6

$300

$5

$250

$4

$200

$3

$150

$2

$100

$1

$50

$-

$-

Source: EDAC

18

EDA / Semi
3.5%

3.0%

2.5%

2.0%

2.2%

1.5%

1.0%

0.5%

0.0%

19

20

6%
21

Software

SDK, IDE, compiler,

debugger, build,
source control

Die

EDA

Package

MCM, EM,
Thermal, Mechanical

Board
Connector

PCB, EM,
Thermal, Mechanical

Sub-System

Mechanical,
Thermal, EM

System

Mechanical, CFD,
Thermal, EM

Ergonomics, sustainability, CO2 emissions

22

Package

MCM, EM

Board
Connector

PCB, EM

23

Hybrid Electromagnetic Simulation

3D

2.5D

3D

24

Hybrid Mode

Return Loss

Insertion Loss
Method
Full 3D
Hybrid 2.D / 3D

Time Per Frequency Peak Memory

61 min

50 GB

6 min

5 GB

Far End Crosstalk

Near End Crosstalk

Hybrid
3D

25

Parallelism in EM Simulation

Layers: 8

Nets: 320

Ports: 1000

IBM Challenge Problem

Capacitance, Inductance of all nets
S-parameter extraction of 20 nets
26

Capacitance Extraction of All Nets

Computation

Time

Speedup

MS&S 8 cores

235 min

6x

RHS

7.3 min

32x

80 machines

Test Case upload

0.7 min

Result download

1.0 min

Peak Memory: 5.5 GB

RHS
Setup time
= 1.8 min (serial)
p = (235-1.8) / 235 = 0.99234

Max Speedup =
N=80

Max Speedup =
n=

1
p
(1-p) +
n
1
p
(1-p) +
n

= 50x

= 131x

27

Inductance Extraction of All Ports

Computation

Time

MS&S 8 cores

Speedup

2741 min

6x

RHS 125 machines

50 min

55x

Test Case upload

1.0 min

Result download

3.0 min

Peak Memory: 14 GB
RHS
Setup time:
= 28 min (serial)
p = (2741-28) / 2741 = 0.98978

Max Speedup =
n=125

Max Speedup =
n=

1
p
(1-p) +
n
1
p
(1-p) +
n

= 55x

= 98x

28

S-Parameters
Computation

Time

MS&S 8 cores

5954 min

RHS
5 machines
Freq 25x5 machines

70 min

Test Case upload

1.0 min

Result download

5.0 min

Speedup
6x
3.4x
25x

Peak Memory: 11 GB
RHS
Setup time
= 11.5 min (serial)
p = (119-11.5) / 119 = 0.8067

Max Speedup =
n=5

Max Speedup =
n=

1
p
(1-p) +
n
1
p
(1-p) +
n

= 3.6x

= 10.3x

29

S-Parameters

Transmission

Reflection

30

Licensing
nCloud supports a flexible licensing model,
ranging from hourly pay-as-you-go softwareas-a-service (SaaS) licensing to longer term
subscriptions such as monthly or annual.
31

Simulation in the Cloud

32

33

Software

SDK, IDE, compiler,

debugger, build,
source control

Die

EDA

Package

MCM, EM,
Thermal, Mechanical

Board
Connector

PCB, EM,
Thermal, Mechanical

Sub-System

Mechanical,
Thermal, EM

System

Mechanical, CFD,
Thermal, EM

Ergonomics, sustainability, CO2 emissions

34

Software
Rank Rank
2013 2012 Vendor

1
2
3
4
5
6
7
8
9
10

1
3
2
4
5
6
7
9
8
12

Microsoft
Oracle
IBM
SAP
Symantec
EMC
HP
VMware
CA Technologies
Salesforce.com
Others
Total

2013
Revenue

2012
Revenue

2012-2013
Growth Rate (%)

65.7
29.6
29.1
18.5
6.4
5.6
4.9
4.8
4.2
3.8
234.6
407.3

62.0
28.7
28.7
16.9
6.4
5.4
5.0
4.2
4.3
2.9
224.0
388.5

6.0
3.4
1.4
9.5
-0.8
4.9
-2.7
14.1
-2.6
33.3
4.7
4.8

Top 10 Worldwide Software Vendors, Worldwide, 2012-2013 (Billions of Dollars)

Source: Gartner (March 2014)

35

CAD / Simulation
$B

Rank Rank
2013 2012

1
2
3
4
5

1
2
3
4
5

Vendor

Dassault Systmes
Autodesk
Siemens PLM
PTC
Ansys
Total

2013
Revenue

2012
Revenue

2012-2013
Growth Rate (%)

2.6
2.3
1.8
1.3
.86
8.9

2.5
2.2
1.7
1.3
.80
8.5

1.8
4.1
7.5
3.0
7.9
4.7

Top 5 Worldwide CAD Vendors, Worldwide, 2012-2013 (Billions of Dollars)

Sources: JPR, Schnittger, Public Co.

36

CAD / Simulation
$B
$10
$9
$8
$7
$6
$5
$4
$3
$2
$1
$2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

37

CAD / Simulation
$B
$10
$9

CAGR = 9.3%

$8
$7
$6
$5
$4
$3
$2
$1
$2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

38

Software

Application
Development $9 / $407B
2.2%
Software

Die
Package

EDA

$.8 / $80B
1.0%

Board
Connector

Sub-System

$6.2 / $303B
2.0%

CAD

>$9 / >2T ?
<0.5%

System

39

40

Summary
Semiconductors and EDA have been
growing at the pace of GWP since 1996
Cost, complexity and functionality
continue to migrate to SW and system
EDA and CAD are poised for contact,
leading to system design
41