STICK DIAGRAMS

P- Diffusion
PMOS Enhancement Transistor
n- Diffusion
Poly silicon

NMOS Enhancement Transistor

Metal 1
Contact cut
N implant
Demarcation line
Substrate contact
Buried Contact

NMOS Depletion transistor

NPN Bipolar Transistor

NMOS INVERTER STICK DIAGRAM

VDD
D

D
A
GND

CMOS INVERTER STICK DIAGRAM

VDD

GND

FIG 1 Supply rails

CMOS INVERTER STICK DIAGRAM

VDD

PMOS

NMOS

GND
Fig 2 Drawing Pmos and Nmos Transistors between Supply rails

CMOS INVERTER STICK DIAGRAM

VDD

PMOS

A
S

NMOS

GND
Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input
With same gate poly silicon metal

CMOS INVERTER STICK DIAGRAM

VDD

PMOS

A
S

NMOS

GND
Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1

CMOS INVERTER STICK DIAGRAM

VDD

PMOS

D
B

A
S

NMOS

GND
Fig 5 Take the output with the poly silicon metal

CMOS INVERTER STICK DIAGRAM

VDD

PMOS
B

A
S

NMOS

GND
Fig 6 Connect the source of Pmos to VDD and Nmos to GND

CMOS INVERTER STICK DIAGRAM

CONTACT

VDD

PMOS
B

A
S

NMOS

GND
Fig 7 Connect the contact cuts where the different metals are connected

CMOS INVERTER STICK DIAGRAM

CONTACT

VDD

PMOS
B

A
S

NMOS

Substrate contact
Fig 8 Final CMOS Inverter

GND

CMOS NAND GATE STICK DIAGRAM

VDD

GND
FIG 9 Supply rails

CMOS NAND GATE STICK DIAGRAM

VDD

GND
Fig 10 Drawing P and N Diffusion between Supply rails

CMOS NAND GATE STICK DIAGRAM

VDD

D
A

D
B
GND

Fig 11 Drawing the poly silicon for two different inputs and
identify the source and drain

CMOS NAND GATE STICK DIAGRAM

VDD

D
A

D
B
GND

Fig 12 Connect the source of Pmos to VDD and Nmos to GND and
subtrate contacts of both

CMOS NAND GATE STICK DIAGRAM

VDD

D
A

D
B
GND

Fig 13 Draw the output connections

CMOS NAND GATE STICK DIAGRAM

VDD

D
A

D
B
GND

Fig 14 Connect the contact cuts where the different metals are connected

LAYOUT

P diffusion

N diffusion
2

P diffusion

N diffusion
1
P diffusion

2
P diffusion

METAL 1
3
METAL 1

4 1

NMOS
ENHANCEMENT
2

NMOS
DEPLETION

PMOS
ENHANCEMENT

2
2

2
2

6 x
6

LAMBDA BSED RULES

CMOS INVERTER
LAYOUT

VDD

VSS

VDD

ND

PD

VSS

VDD

ND
D

P
O
L
Y
D

S
PD

VSS

VDD

ND
S

P
O
L
Y

S
PD

VSS

VDD
SUB
CONT
ND

INPU
T

P
O
L
Y

OUTPU
T

PD

VSS
SUB
CONT

CMOS NAND
LAYOUT

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD
SUB
CONT
D

VSS
SUB
CONT

VDD
SUB
CONT
D

OUTPU
T

VSS
SUB
CONT

Scaling
VLSI technology is constantly evolving towards
smaller line widths
Reduced feature size generally leads to
better / faster performance
More gate / chip
More accurate description of modern technology is
ULSI (ultra large scale integration)

Characteristics Of
Technology:
Minimum feature size
No. of gates on one chip
Power dissipation
Maximum operation frequency
Die Size
Production cost

Scaling Factors
In our discussions we will consider 2 scaling
factors, and
1/ is the scaling factor for VDD and oxide
thickness tox
1/ is scaling factor for all other linear
dimensions.

Scaling Factors for Device Parameters :

It is important that you understand how the
following parameters are effected by scaling.
Gate Area
Gate Capacitance per unit
area
Gate Capacitance
Charge in Channel
Channel Resistance
Maximum Operating
Frequency

Transistor Current
Transistor Delay
Switching Energy
Power Dissipation Per
Gate (Static and
Dynamic)
Power Dissipation Per
Unit Area
Power - Speed Product

MOSFET Scaling
SCALING - refers to ordered reduction in dimensions of
the MOSFET and other VLSI features

Reduce Size of VLSI chips.

Change operational characteristics of MOSFETs and

parasitic.

Physical limits restrict degree of scaling that can be

achieved.

Methods of Scaling:
1) Constant Field Scaling
2) Constant Voltage Scaling
3) Lateral Scaling

1.Constant Field Scaling

The electric field E is kept constant, and the
scaled device is obtained by applying a dimensionless
scale-factor a (such that E is unchanged):

all dimensions, including those vertical to the

surface (1/)

device voltages (1/)

the concentration densities ().

2. Constant Voltage Scaling

Vdd is kept constant.

All dimensions, including those vertical to the

surface are scaled.

Concentration densities are scaled.

3. Lateral Scaling
Only the gate length is scaled L = 1/a (gate-shrink).
Year
1980
1983
1985
1987
1989
1991
1993
1995

Feature Size(mm)
5.0
3.5
2.5
1.75
1.25
1.0
0.8
0.6

DERIVATION OF SCALING PARAMETERS :

1.Gate Area( Ag) :

Before Scaling:
After Scaling :

Area is reduced by 2,
it is advantage.

2. Gate Capacitance per unit area ( Co or

Cox ):
Before Scaling:
ox - permittivity of gate oxide
tox gate oxide thickness
After Scaling :

Cox is scaled by

3. Gate Capacitance (Cg ):

Before Scaling:

After Scaling :

Cg is scaled by
/2

4. Parasitic Capacitance (Cx ):

Before Scaling : Cx is proportional to Ax / d
where d depletion width around source & drain
which is scaled by 1/ .
Ax area of depletion region around source
& drain which is scaled by 1/2
After Scaling :

Cx is scaled by
1/

5.Charge in Channel QON :

Before Scaling:
QON avg charge per unit area in the channel in the
ON state

After Scaling :

QON is scaled by
1

6. Channel Resistance (RON ):

Before Scaling:
After Scaling :
- Constant

RON is scaled by
1

7.Gate delay (Td) :

Before Scaling:
After Scaling :

Td is scaled by /
2

8. Maximum Operating Frequency

fo :
Before Scaling:

After Scaling :
As Td Scaled by / 2
fo is scaled by 2 /

9. Saturation Current (Idss) :

Before Scaling:
After Scaling :

Ids is scaled by 1/

10. Current Density (J) :

Before Scaling:
After Scaling :

J is scaled by 2/

11. Switching energy per gate

(Eg) :
Before Scaling:
After Scaling :

Eg is scaled by
1/2

12 . Power dissipation per gate

(Pg) :
Before Scaling:
Static Component
Dynamic Component
After Scaling :

Pg is scaled by 1/2

13. Power dissipation per unit area

(Pa) :
Before Scaling:
After Scaling :

Pa is scaled
by 2/2

14. Power Speed Product (PT) :

Before Scaling:
After Scaling :

PT is scaled by
1/2

PARAMETER

SCALING MODEL
Constant Constant Lateral
Field
Voltage
Length (L)
1/ 1/ 1/
Width (W)
1/ 1/
1
Supply Voltage (V)
1/ 1
1
Gate Oxide thickness (tox)
1/ 1/
1
Junction depth (Xj)
1/ 1/ 1
Current (I)
1/

Power Dissipation (P)

1/

Electric Field
1

1
Load Capacitance (C)
1/1/
1/
Gate Delay (T)
1/1/ 1/

Scaling of Interconnects
Resistance of track R ~ L / wt
R (scaled) ~ (L / ) / ( (w/ )* (t
/))
R(scaled) = R
therefore resistance increases with
scaling

Scaling - Time Constant

Time constant of track connected to gate,

T = R * Cg
T(scaled) = R * ( / 2) *Cg = ( / ) *R*Cg
Let = , therefore T is unscaled!
Therefore delays in tracks dont reduce with scaling
Therefore as tracks get proportionately larger, effect gets worse
Cross talk between connections gets worse because of reduced
spacing

Scaling of MOS and circuit parameter