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Slide 3-1
Oxidation
Lithography &
Etching
Ion Implantation
Annealing &
Diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-2
Flow
controller
O2 N 2
H 2O or TCE(trichloroethylene)
Resistance-heated furnace
Slide 3-3
Si + O2 SiO2
Wet Oxidation :
Slide 3-4
Slide 3-5
3.3 Lithography
(a) Resist
(c)
Coating
Positive resist
Photoresist
Si
Negative resist
Oxide
(b) Exposure
Si
Development
(d)
Si
Photomask with
opaque and
clear patterns
Si
Si
Slide 3-6
3.3 Lithography
Photolithography Resolution Limit, R
Slide 3-7
3.3 Lithography
Wafers are being loaded into a stepper in a clean room.
Slide 3-8
Photo Mask
Water
Photoresist
Wafer
(a)
(b)
Slide 3-9
Slide 3-10
Slide 3-11
Anisotropic etching
photoresist
photoresist
SiO 2
SiO 2
(1)
(1 )
p h o to r es ist
p h o t o re si s t
SiO 2
SiO 2
(2)
SiO 2
(2)
SiO 2
(3)
(3)
Modern
Semiconductor
Circuits
Hu)
(a) Isotropic
wet etching Devices for Integrated
(b) Anisotropic
dry(C.
etching.
Slide 3-12
Wafers
Gas Inlet
RF
Vacuum
RF
Cross-section View
Top View
Slide 3-13
Slide 3-14
Slide 3-15
3.5 Doping
3.5.1 Ion Implantation
Dopant ions
Slide 3-16
Slide 3-17
Slide 3-18
Ni : dose (cm-2)
R : range or depth
R : spread or sigma
Slide 3-19
Slide 3-20
n-type
diffusion layer
p-type Si
No
x 2 / 4 Dt
N ( x, t )
e
Dt
N : Nd or Na (cm-3)
No : dopant atoms per cm2
t : diffusion time
D : diffusivity, Dt is the approximate distance of
dopant diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-21
Slide 3-22
Slide 3-23
Example:
Silicon wafer
Polycrystalline
Amorphous
Thin film of
SiO2 or Si3N4.
Slide 3-24
Slide 3-25
3.7.1 Sputtering
Schematic Illustration of Sputtering Process
Sputtering target
Ion (Ar +)
Target material
deposited on wafer
S i W a fe r
Slide 3-26
Slide 3-27
Slide 3-28
Slide 3-29
Resistance-heated furnace
Quartz tube
Trap
To exhaust
Si Wafers
Pump
Gas control
system
Source
gases
LPCVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-30
Gas Injection
Ring
Wafers
Pump
Heater Coil
Wafers
Pump
Gas
Inlet
Power leads
Plasma Electrodes
PECVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-31
Selective Epitaxy
SiO2
Si Substrate
Epi film
Si Substrate
(a)
SiO2
Si Substrate
SiO2
E p i f il m
SiO2
Si Substrate
(b)
Slide 3-32
Si
(a)
Encapsulation
M etal 3
Dielectric
Me tal 2
via or plug
Dielectric
M etal 1
Dielectric
CoSi2
silicide
Si
diffusion region
(b)
Slide 3-33
Slide 3-34
Slide 3-35
dielectric
dielectric
(a)
Chemical-Mechanical
Polishing (CMP)
removes unwanted
materials.
(b)
Cu
Cu
liner
liner
dielectric
dielectric
(c)
(d)
Slide 3-36
Slide 3-37
Slide 3-38
P-Si
(3)
SiO2
(11)
SiO2
P-Si
3.10 Chapter SummaryA Device Fabrication
Example
Arsenic implantation
Wafer
(0)
(4)
P-Si
(8)SiO
S iO2
P-Si N
Ion
Implantation
SiO
Al
SiO2 S iO
2
SiO2
(1 )
P-Si
Oxidation
(5)
SiO2
UV
(3)
(6)
Annealing &
Al
SiO Diffusion
2
P 2
SiO
N
P Si
N4
3
SiO2 UV
M as k
P-Si
Al
UV
SiO2
(7)
(11)Res is t
Si3 N4
SiO2
N+
SiO2
(4)
SiO2
A l
SiO2
Al
SiO 2
SiO2
P-Si
Modern Semiconductor
Devices for Integrated Circuits (C. Hu)
(12)
(5)
SiO 2
SiO2
SiO2
Si3 N4
Si
(13)
N+
SiO2
Al
Sputtering
Photoresist
Al
Arsenic implantation
SiO
N+
(10)
P-Si
Etching
N4
A l
SiO2
Positive resist
SiO2
SiO2
SiO2
M ask
Lithography
+
NSi
SiO2
UV
(2)
SiO 2
(9)
(12)
Lithography
Slide 3-39
Al
SiO2
(3)
SiO2
P-Si
Si3 N4
Al
Arsenic implantation
(4)
SiO
SiO
3.10 Chapter SummaryA Device
Fabrication
Example
2
SiO2
Metal
etching
Al
S iO2
S iO2
(12)
N+
P SiO2
SiO 2
N+
(9)
CVD
nitride
(6)
deposition
SiO2
P-Si
(8)
(5)
SiO2
SiO2
N SiO2
wire
Si3 N4
UV
Al
SiO2
SiO2
+
M as kN
(11) Al
Photoresist
SiO2
SiO2
SiN3 N4
P
A l
SiO 2
N
SiO2
+
Au
Plastic package
Al
SiO2
Al
SiO2
Back Side
milling
Si3N 4
(13)
Res is t
Au
(10)
Lithography
and etching
Al
+
SiO 2
metal leads
(12)
Back side
metallization
N+
Si3 N4
A l SiO2
SiO2
Si3 N4
Al
(7)
Si3 N4
Modern Semiconductor
Al Devices for Integrated Circuits (C. Hu)
SiO2
SiO 2
N+
Slide 3-40