Chapter 12

Controller Design (to determine controller

settings for P, PI or PID controllers) Based
on Transient Response Criteria

Chapter 12

Desirable Controller Features

1. The closed-loop system must be stable.
2. The effects of disturbances are minimized, i.e., good
disturbance rejection.
3. Quick and smooth responses to the set-point changes are
guaranteed, i.e., good set-point tracking.
4. Off-set is eliminated.
5. Excessive controller action is avoided.
6. The control system is robust, i.e., it is insensitive to
changes in operating conditions and to inaccuracies in
process model and/or measurements.

Chapter 12

Simplified Block Diagram

Y s

K mGc s Gv s G p s

1 Gc s Gv s G p s Gm s

Gm s Y s

Ysp s

K mGc s Gv s G p s Gm s

1 Gc s Gv s G p s Gm s

Gd s
D s
1 Gc s Gv s G p s Gm s

Ysp s

Gd s Gm s
D s
1 Gc s Gv s G p s Gm s

let
G1 s Gv s G p s Gm s
G2 s Gd s Gm s
B s

Gc s G1 s %
G2 s
Ysp s
D s
1 Gc s G1 s
1 Gc s G1 s

Simplified Block Diagram

D(s)

Y%
sp s

P(s)

G1 s Gv s G p s Gm s
G2 s Gd s Gm s

B(s)

Example
1
G1 s Gv s G p s Gm s
e 4 s
20 s 1
G2 s Gd s Gm s 1

1
Gc s K c 1
I s

1
D s
s

Chapter 12

Example 12.1

Chapter 12

Chapter 12

Chapter 12

Alternatives for Controller Design

1.
2.
3.
4.
5.
6.

Direct synthesis (DS) method

Internal model control (IMC) method
Controller tuning relations
Frequency response techniques
Computer simulation
On-line tuning after the control system is installed.

Direct Synthesis
K mGc Gv G p
Y

Ysp 1 GcGvG p Gm
Let G Gv G p Gm and Gm K m
GC G
Y

Ysp 1 GC G

1 Y / Ysp
Gc

G 1 Y / Ysp

Let
G G% assumed process model
Y Y
desired closed-loop transfer function
Ysp Ysp
d

1 Y / Ysp d

Gc
%
G 1 Y / Ysp
d

Direct Synthesis Steps

1. Specify desired closed-loop response
(transfer function)
2. Assume process model
3. Solve for controller transfer function

Direct Synthesis to Achieve Perfect

Control
Y
Case 1: Desired response is 1
Y
sp
d

Y
This is impossible since 1- 0
Y
sp
d

Y
Kc
Case 2:
, i.e., an offset is allowed
Y
1

K
c
sp
d

Gc

Ex. G%

Kc
G%
K
1s 1 2 s 1

Gc

Kc
1 2 s 2 ( 1 2 ) s 1
K

This is not practical!

Direct Synthesis to Achieve Finite

Settling Time
Y
1

(Note that there is no offset!)

cs 1
Ysp
d

1
1 cs 1
1 1
Gc s

G%1 1
G% c s
cs 1
1 1
%
Ex 1: G K Gc s
(pure integral controller)
K c s

Example
K
%
G s
s 1
1 1 s 1 1
Gc s %
G cs
K cs

1
K c
s

PI controller: K c
, I
K c

Example
G% s

K
1s 1 2 s 1

1 2 s 2 1 2 s 1 1
Gc s
K
cs
1 2
Gc s
K c

1 2
1

1
1 2 s 1 2

Parallel PID controller:

Kc

1 2

; I 1 2 ; D 1 2
K c
1 2

1
1
Gc s
1 2 s 1
K c
1s
Series PID controller:

K c 1 ; I 1 ; D 2 ; =0
K c

Direct Synthesis for TimeDelayed Systems

%
G% s G% s e s
Y
1
c s

e
; c

Y
cs 1
sp

d

Let c
s
1
e
1
1
%
Gc s %
%
s
s
%
G s cs 1 e

e
G s c

Taylor Series Approximation

e

1
2
1 s s L 1 s
2!
s

1
e
Gc s
G% c s 1 1 s
1
1

%
G% c s

Example 1
K s
%
s
%
%
G s G s e
e
s 1
s 1
1

Gc s

K c s K c

1
1
s

PI controller: K c
, I
K c

Example 2
%
G% s G% s e s

Gc s

K
e s
1s 1 2 s 1

1s 1 2 s 1

1 2
K c

1
c s

1
1 2
1

1 2 s 1 2

Parrallel PID controller:

Kc 1 2 ; I 1 2 ; D 1 2
K c
1 2

Pade Approximation
e

1 / 2 s

1 / 2 s

1
e s
Gc s
1 / 2 s
G%
cs 1
1 / 2 s
e s 1 / 2 s
1

G% 1 / 2 s c s 1 1 / 2 s
1 / 2 s
1

%
G% 1 / 2 s c s 1 1 / 2 s

Example
K s
%
G% s G% s e s
e
s 1
1 / 2 s
s 1
Gc s
K 1 / 2 s c s 1 1 / 2 s

1
K c
s

1 / 2 s

c
s 1
2c

1
1 D s
Series PID controller: Gc s K c 1

I
D 1
c

Kc
, I , D ,
K c
2
c

Chapter 12

Example 12.1
Use the DS design method to calculate PID controller settings for
the process:
2e s
G
10s 1 5s 1

Chapter 12

Consider three values of the desired closed-loop time constant:

. Evaluate the controllers for unit step
c 1, 3, and 10
changes in both the set point and the disturbance, assuming that
Gd = G. Repeat the evaluation for two cases:
a. The process model is perfect ( G%= G).
b. The model gain is K%= 0.9, instead of the actual value, K = 2.
Thus,

s
0.9
e
G%
10s 1 5s 1

The controller settings for this example are:

Kc
Kc
I
D

K% 2
K% 0.9

c 1

c 3

c 10

3.75

1.88

0.682

8.33

4.17

1.51

15
3.33

15
3.33

15
3.33

Chapter 12
Figure 12.3 Simulation results for Example 12.1 (a): correct
model gain.

Simulation results for Example 21.1(b): incorrect model gain.

Chapter 12

PID vs. IMC

Gc G
1
PID:Y
Ysp
D
1 Gc G
1 Gc G
IMC: Y

Gc*G

1 G Gc G%
*
c

Ysp

1 Gc*G%

Gc*
G
* %
1 Gc G
1
Y
Y

D
sp
*
*
Gc
Gc
1
G
1

G
* %
* %
1 Gc G
1 Gc G
Gc*
Gc
1 Gc*G%

1 G Gc G%
*
c

PID Controller Design Procedure

Based on IMC Method Step 1:
factor process model
%
G% G%
G

where
G% g time delays, positive zeros

%%
G%
G / G
Note that
G% | 1 steady-state gain
s 0

PID Controller Design Procedure

Based on IMC Method Step 2:
derive IMC transfer function
1
G
f
%
G
*
c

where
f

c s 1

a low-pass filter with a steady-state gain of one

c the desired closed-loop time constant

r a positive integer (usually 1)

PID Controller Design Procedure

Based on IMC Method Step 3:
derive PID transfer function
*
c
*
c

G
Gc
1 G G%

Chapter 12

Example
K s
G% s
e
s 1
1/1 Pade approximation

s
K
2
G% s
s 11 s
2

1
% s K
G%
s

s
;
G

2
s 1 1 s
2

1
1

Gc* s
f
K
1

Select f

1
cs 1

1
1

1

2

K
c s 1

Gc*
Gc

* %
1 Gc G

1
1

1 K 1 s

2

1
K
c s 1 s 1 1 s

1
1 1

2

s
1

K
s 2
c
2
2

1
2 ; ;
Kc
I
D
K
2
2
c
2

Controller Synthesis Criteria in

Time Domain
Time-domain techniques can be classified into
two groups:
(a) Criteria based on a few points in the
response
(b) Criteria based on the entire response, or
integral criteria

Approach (a)
Based on settling time, % overshoot, rise time,
decay ratio (Fig. 5.10 can be viewed as closedloop response).
Several methods based on 1/4 decay ratio have
been proposed, e.g., Cohen-Coon and ZieglerNichols.

2
1

Decay Ratio exp
2

4
1

1
Overshoot exp

2
1 2

0.2

Chapter 12

Chapter 12
Ke s
Based on assumed open-loop model: GOL ( s)
1 s

(FOPDT)

Approach (b) - Criteria

Integral of absolute value of error (IAE)

IAE e(t ) dt
0

Integral of square error (ISE)

ISE e(t ) dt
2

Time-weighted IAE (ITAE)

ITAE t e(t ) dt
0

Approach (b) - Remarks

Pick controller parameters to minimize integral.
1. IAE allows larger overall deviation than ISE
(with smaller overshoots).
2. ISE needs longer settling time
3. ITAE weights errors occurring later more heavily
Approximate optimum tuning parameters are
correlated with K, , (Table 12.3).

Chapter 12

Chapter 12

Example 1
10 s
%
G s
e Design a PI controller for load change
2s 1
Use ITAE criterion

10 K c 0.859

0.674
I

0.977

1.69

K c 0.169

0.680

1.08

I 1.85

Example 1

Kc

ITAE

0.169

1.85

IAE

0.195

2.02

ISE

0.245

2.44

Example 2
G% s

4 3.5 s
e
7s 1

(a) design for load changes (aggrssive)

large overshoot for set-point changes
(b) design for set-pont changes (conservative)
sluggish response to load disturbances

Chapter 12

Summary of Tuning Relationships

Chapter 12

1. KC is inversely proportional to KPKVKM .

2. KC decreases as / increases.
3. I and D increase as / increases (typically D =
0.25 I ).
4. Reduce Kc, when adding more integral action;
increase Kc, when adding derivative action
5. To reduce oscillation, decrease KC and increase I .

Disadvantages of Tuning Correlations

Chapter 12

1. Interactions are ignored (decreased stability limits).

2. Derivative action equipment specific.
3. First order + time delay model can be inaccurate.
4. Kp, can vary.
5. Resolution, measurement errors decrease stability
margins.
6. decay ratio not conservative standard (too
oscillatory).

Example 12.4

Chapter 12

Consider a lag-dominant model with / 0.01:

G% s

100 s
e
100 s 1

Design four PI controllers:

a) IMC c 1
b) IMC c 2 based on the integrator approximation in Eq. 1233
c) IMC c 1 with Skogestads modification (Eq. 12-34)
d) Direct Synthesis method for disturbance rejection (Chen and
Seborg, 2002): The controller settings are Kc = 0.551 and
I 4.91.

Evaluate the four controllers by comparing their performance for

unit step changes in both set point and disturbance. Assume that
the model is perfect and that Gd(s) = G(s).

Chapter 12

Solution
The PI controller settings are:
Controller

Kc

(a) IMC

0.5

100

(b) Integrator approximation

0.556

(c) Skogestad

0.5

(d) DS-d

0.551

4.91

Chapter 12

Figure 12.8. Comparison

of set-point responses
(top) and disturbance
responses (bottom) for
Example 12.4. The
responses for the Chen
and Seborg and integrator
approximation methods
are essentially identical.

Chapter 12

On-Line Controller Tuning

Chapter 12

1. Controller tuning inevitably involves a tradeoff between

performance and robustness.
2. Controller settings do not have to be precisely determined. In
general, a small change in a controller setting from its best
value (for example, 10%) has little effect on closed-loop
responses.
3. For most plants, it is not feasible to manually tune each
controller. Tuning is usually done by a control specialist
(engineer or technician) or by a plant operator. Because each
person is typically responsible for 300 to 1000 control loops, it
is not feasible to tune every controller.
4. Diagnostic techniques for monitoring control system
performance are available.

Chapter 12

Controller Tuning and

Troubleshooting Control
Loops

Ziegler-Nichols Rules:

Chapter 12

These well-known tuning rules were published by Z-N

in 1942:
controller
P
PI
PID

Kc

0.5 KCU
0.45 KCU

PU/1.2

0.6 KCU

PU/2

D
PU/8

Z-N controller settings are widely considered to be an

"industry standard".
Z-N settings were developed to provide 1/4 decay
ratio -- too oscillatory?

Chapter 12

Modified Z-N settings for PID control

I

controller

Kc

original
Some overshoot
No overshoot

0.6 KCU

PU/2

PU/8

0.33 KCU

PU/2

PU/3

0.2 KCU

PU/3

PU/2

Chapter 12

K CU
4d

Chapter 12

Chapter 12
Figure 12.15 Typical process reaction curves: (a) non-selfregulating process, (b) self-regulating process.

Chapter 12
Figure 12.16 Process reaction curve for Example 12.8.

Chapter 12
Figure 12.17 Block diagram for Example 12.8.

Chapter 12