VMWARE BASICS

BY
DUDDALA RAJANBABU

Hypervisor:

Ahypervisoror virtual machine monitor

(VMM) is a piece of computer software,
firmware or hardware that creates and runs
virtual machines. A computer on which
ahypervisoris running one or more virtual
machines is defined as a host machine.
Each virtual machine is called a guest
machine.

CLUSTER:
Aclusteris a group of hosts. When a host is
added to acluster, the host's resources
become
part
of
thecluster'sresources.
Thecluster manages the resources of all hosts
within it.Clustersenable the vSphere High
Availability (HA) and vSphere Distributed
Resource Scheduler (DRS) solutions.

REGULAR 16BIT SQRT CSLA

DELAY AND AREA EVALUATION OF THE BASIC ADDER

BLOCKS
The AND, OR, and Inverter (AOI) implementation of an XOR
gate.

The gates between the dotted lines are

performing the operations in parallel
and the numeric representation of each
gate indicates the delay contributed by
that gate.

AREA EVALUATION METHODOLOGY OF REGULAR 16-b SQRT

CSLA
Gate count=
57(HA+FA+MUX)
FA=39(3*13)
HA=6(1*6)
MUX=12(3*4)

PROBLEMS IN EXISTING SYSTEM

The problem in CSLA design is the number of full adders are increased then
the circuit complexity also increases.
The number of full adder cells are more thereby power consumption of the
design also increases

SOLUTION OF THE PROBLEM

The parallel RCA with Cin=1 is replaced with Binary-Excess 1 converter( BEC).

four-bit BEC

Modified CLSA
Basic function of CLSA is obtained by using the 4-bit BEC together with the mux.

PROPOSED SYSTEM(16-b CLSA)

Contd
In this system we use the BEC to reduce the RCA circuits
Here based on the carry input the MUX will be select corresponding input
In this design we give the MUX inputs are RCA output and BEC output
Compare to regular design the area of the design is less

AREA EVALUATION METHODOLOGY OF MODIFIED 16-b

SQRT CSLA
GATE COUNT=
41(HA+FA+MUX+BEC)
(13+6+12+10)

COMPARISION
GROUP

REGULAR

MODIFIED

GROUP 2

57

43

GROUP 3

84

61

GROUP 4

117

84

GROUP 5

147

107

RTL SCHEMATIC

Simulation Result
Carry select adder existing system

Simulation Result
Carry select adder proposed system For 16 bit

SynthesisResult

TOOL USED
Programming language: VERILOG HDL
Tool : Xilinx ISE (10.1)

ADVANTAGES
Low power consumption
Less area (less complexity)
More speed compare regular CSLA

APPLICATIONS
Arithmetic logic units
High Speed multiplications
Advanced microprocessor design
Digital signal process

CONCLUSION
A simple approach is proposed in this paper to reduce the area and power
of SQRT CSLA architecture. The reduced number of gates of this work offers the
great advantage in the reduction of area and also the power. The modified CSLA
architecture is therefore, low area, low power, simple and efficient for VLSI
hardware implementation.

REFERENCES
[1] B. Ramkumar, Harish M Kittur Low power and Area efficient carry select adder,IEEE
Trans,Vol.20,Feb 2012.
[2] T. Y. Ceiang and M. J. Hsiao, Carry-select adder using single ripple carry adder, Electron.
Lett., vol. 34, no. 22, pp. 21012103, Oct. 1998.
[3] Y. Kim and L.-S. Kim, 64-bit carry-select adder with reduced area, Electron. Lett., vol.
37, no. 10, pp. 614615, May 2001.
[4] J. M. Rabaey, Digtal Integrated CircuitsA Design Perspective.Upper Saddle River, NJ:
Prentice-Hall, 2001.
[5]

Samir Palnitkar, Verilog Hdl: A Guide to Digital Design and Synthesis2005,2 nd Edition.