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CMOS TECHNLOGY

BOOSTERS

Outline
Classical
Driving

factors for introduction to Technology Boosters

Strained
High

Scaling

Silicon Technology

K Dielectrics in CMOS

Polysilicon

to Metal Gates

The Golden Era of Scaling

Dennard Scaling (Classical scaling)

From [2]
Device or Circuit Parameter

Transistor
Area
The first
description

Scaling Factor

2
of transistor scaling was1/given
by Robert H. Dennard in his classical paper of 1974 [1]

Based on the concept of maintaining constant electric


filed in a transistor
2

Power dissipation/circuit VI
Power density VI/A

1/
1

Helped Gordon Moores concept of Just pack them closer on a chip

Maintains power density per chip even with increased number of transistors

The Golden Era of Scaling

The cmos technology experienced very few changes in the standard


cmos process

The Silicon Silicon dioxide interface is said to be the driving force


behind the success of silicon industry

The so called era of classical scaling finally ended with silicon


dioxide scaling limitations

Driving factors for introduction to


new Performance Boosters

The sub100 nm technology required SiO 2 thickness scaled to around 3nm and less,
few monolayers of SiO2 atoms

At such thickness of SiO 2 the gate leakage current started to dominate leading to
increased passive power consumption

[3]

[4]

Driving factors for introduction to


new Performance Boosters

Threshold Voltage variations

Improve response against Short Channel effects

Follow the desired growth rate

ITRS in 2004 update indicated some emerging technologies and


new materials as Technology Performance Boosters capable of
integrating with existing CMOS facilities and maintaining the
expected growth of the industry [5]

Mobility Degradation in channel

Reduction in gate control due to increased lateral electric fields

To gain better gate control substrate doping is increased

Enhanced gate control at the cost of reduced effective mobility of charge


carriers

[ Bart Van Zeghbroeck - http://ecee.colorado.edu/~bart/book/mobility.htm ]

Strained Silicon Technology

First commercial introduction of technology by intel in 2002 with HT Prescott P4 Processor

Increase in effective carrier mobility

Considerable improvement in hole mobility as compared to electron mobility

[6]

Strained Silicon Technology

Use the lattice mismatching of silicon and germanium to introduce strain (Ge5.658A & Si- 5.431A)

Introduces Bidirectional strain

Magnitude of strain can be controlled with the Germanium contents

[7]

Strained Silicon Technology

Mobility enhancement for Electron

[8]

[9]

The inversion layer energy bands split into subbands under strain

Increased electron density at E2 valleys with lower effective mass

Reduction in intervalley electron transfer due to absorption of phonons

Strained Silicon Technology

Mobility enhancement for holes

[10]

The valence band of silicon has different energy states with difference
between the effective masses

On Strain the split off band moves away from the hole bands hence reduced
probabilities of interband scattering events

The light hole band moves to the top of the valence band

Strained Silicon Technology

[11]

[12]

Global strain

Local or Process induced strain


eSiGe/eSiC

SMT

CESL

SOI has emerged as a new promising platform for strained silicon technology

Process compatibility and localized heating were two major issues of strained
silicon technology

High Permittivity (K) Dielectrics


Promising
Must

in reducing leakage current maintaining the capacitance density

show process compatibilities to existing cmos facilities

Most

promising materials
Aluminum oxide (Al2O3)
Yttrium oxide (Y2O3)
Titanium oxide(TiO2)
Zirconium oxide (ZrO2)
Hafnium oxide (HfO2)
Tantalum oxide (Ta2O5)
Lanthanum oxide (La2O3)
Strontium titanate (SrTiO3)
[13]

High Permittivity (K) Dielectrics


Criteria

for selection

Process
Large

compatibility

bandgap

High

enough Permitivity next few generations


of technology

High

quality channel interface and defects

Inert

to silicon and gate materials

Thermodynamic

Stability

High Permittivity (K) Dielectrics


Popular

Deposition Techniques

[14]

Polysilicon to Metal gates


Intel

introduced metal gates with high k dielectric


stack in their 45nm technology in 2007

Depletion

[15]

of polysilicon layer

Polysilicon to Metal gates

Poly high k interface had more detects at interface increasing soft optical
phonons and thus scattering mechanism

Degradation of carrier mobility

[16]

Metal Gate

Thermal compatibility to process and High k

Must meet required work function for threshold voltage control

Options Available for metal gate

Metals

Alloys

Metal Nitrides

Metal Silicides

Shifting from Gate first to Gate


To adapt high K Metal gate stack after a long time considerable change in
Last
standard cmos process flow

Process flow for Intel 45nm Node (Gate last Process)


STI, Wells and VT Implants
ALD deposition of High K Dielectric
Polysilicon deposition and gate patterning
S/D extensions, spacer, Si Recess & SiGe deposition
S/D formation, Ni Salicidation, ILDO deposition
Poly Opening Polish, Poly Removal
PMOS workfunction metal deposition
Metal Gate patterning, NMOS WF metal deposition
Metal gate fill and polish, ESL deposition

[15]

Success of Technology Boosters

[17]

[18]

Thank You

Questions ?
?

References
[1] Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, Andre R.
Leblanc, Design of Ion-Implanted MOSFETS with Very Small Physical Dimensions, IEEE Journal
of Solid State Circuits, October 1974.
[2] B. Davari, R. H. Dennard, and G. G. Shahidi, CMOS scaling for high-performance and lowpowerthe next ten years, Proc. IEEE, vol. 89, pp. 595606, Apr. 1995.
[3] Y. Taur, CMOS design near the limit of scaling, IBM Journal of Research and Development;
Mar/May 2002; 46, 2/3; ABI/INFORM Complete
[4] W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X.
Wang, J. B. Johnson, M. V. Fischetti, Silicon CMOS devices beyond scaling, IBM J. RES. & DEV. VOL.
50 NO. 4/5 JULY/SEPTEMBER 2006
[5] The International Technology Roadmap for Semiconductors: 2004 Update (Emerging Research
Devices)
[6] Mark Bohr, The Invention of Uniaxial Strained Silicon Transistors at Intel, (Source:
http://download.intel.com/pressroom/kits/advancedtech/pdfs/Mark_Bohr_story_on_strained_silicon.pdf)
[7] Minjoo L. Lee, Eugene A. Fitzgerald, Mayank T. Bulsara, Matthew T. Currie, Anthony Lochtefeld,
Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect
transistors, J. Appl. Phys. 97, 011101 (2005); http://dx.doi.org/10.1063/1.1819976

References
[8] Shin-Ichi Takagi, Two-dimensional Carrier Transport in Si MOSFETs, VLSI DESIGN 1998,
Vol. 8, Nos. (1-4), pp. 1-11

[9] Dimoulas, A., Gusev, E., McIntyre, P.C., Heyns, M. (Eds.), Advanced Gate Stacks for HighMobility Semiconductors, Springer Series in Advanced Microelectronics

[10] K. Rim, R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen,S. Christansen , J. Chu, K. Jenkins,
T. Kanarsky, S. Koester, B.H. Lee, K. Lee, V. Mazzeo, A. Mocuta, D. Mocuta, P.M. Mooney, P.
Oldiges, J. Ott, P. Ronsheim, R. Roy, A. Steegen, M. Yang, H. Zhu, M. Ieong, H.-S.P. Wong, Strained
Si CMOS (SS CMOS) technology: opportunities and challenges, Solid-State Electronics 47
(2003) 11331139
[11] Yongke Sun, Scott E. Thompson, Toshikazu Nishida, Strain Effect in Semiconductors, ISBN
978-1-4419-0551-2, DOI 10.1007/978-1-4419-0552-9 Springer
[12] S.dhar, Analytical Mobility Modeling for Strained Silicon-Based Devices,
(Sourse:http://www.iue.tuwien.ac.at/phd/dhar/)
[13] John Robertson, High dielectric constant gate oxides for metal oxide Si Transistors,
Rep. Prog. Phys. 69 (2006) 327396 doi:10.1088/0034-4885/69/2/R02

References
[14] Robert D. Clark, Emerging Applications for High K Materials in VLSI Technology,
Materials 2014, 7, 2913-2944; doi:10.3390/ma7042913

[15] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A.


Cappellani, R. Chau, C.-H. Choi,G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M.
Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly,P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K.
Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae,C. Parker, D. Parsons, C.
Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple,D.
Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, A
45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon,9 Cu
Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, 1-4244-0439X/07/$25.00 2007 IEEE

[16] Tsu-Jae King, Integrated Circuit Devices - lecture notes EE130(Spring 2003),
Electronics SupportGroup (EECS), University of California, Berkeley

[17] Kelin J. Kuhn and Anand Murthy, Present and Future: SiGe and CMOS Transistor
Scaling, Abstract #1853, 218th ECS Meeting, 2010 The Electrochemical Society.

[18] Kaizad Mistry, Transistor Scaling: The age of innovation, Source Intel Corporation

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