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For PMOS
VSG > |VTP|
VSD sat = VSG + VTP
Electronics
Electronics
NMOS
PMOS
o VTN is POSITIVE
o VGS > VTN
to
turn on
o Triode/nonsaturation region
o VTP is NEGATIVE
o VSG > |VTP| to turn
on
o Triode/nonsaturation region
o Saturation region
o Saturation region
Electronics
DC analysis of FET
Electronics
- NMOS
R2
R1 + R2
VDD
2.
3.
4.
5.
Electronics
EXAMPLE:
Calculate the drain current and drain to source voltage of a common source
circuit with an n-channel enhancement mode MOSFET. Assume that R1 = 30
k, R2 = 20 k, RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2
VTH =
20
30 + 20
VDSsat = VGS VTN = 2 1 = 1V, so, VDS > VDSsat, our assumption
that the transistor is in saturation region is correct
Electronics
EXAMPLE
The transistor has
parameters VTN = 2V and
Kn = 0.25mA/V2.
Find ID and VDS
VDD =
10V
R1 =
280k
R2 =
160k
Electronics
RD =
10k
Solution
1. VTH =
160
3.636 V 160 + 280
10 =
PMOS
Different notation:
VSG and VSD
Threshold Voltage = VTP
VG = VTH =
R2
R1 + R2
Electronics
VDD
- PMOS
ID = Kp (VSG + VTP)2
Calculate VSD:
Use KVL at DS loop:
VSD + IDRD - VDD = 0
If VSD > VSD(sat) = VSG + VTP, then the transistor is biased in the
saturation region.
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7.5 k
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56.25 I
50.67 I + 11 = 0
ID = 0.365
mA
ID = 0.536 mA
ID = 0.365
mA
LOAD LINE
Common source configuration i.e
source is grounded.
It is the linear equation of ID versus VDS
Use KVL
VDS = VDD IDRD
ID = -VDS + VDD
RD
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RD
ID (mA)
yintercept
ID
QPOINTS
VDS
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VGS
xintercept
VDS (V)
Electronics
use KVL:
0 + VGS+ 1(ID) -5 +1
=0
VGS = 4 - ID
2. Assume in saturation
Electronics
Replace in
VGS
equation
VGS = 4 - ID
ID = 6.646
mA
Why choose VGS = 2.646 V ?
Because it is bigger than VTN
VGS =
2.646 V
VGS= -2.
646 V
ID
Electronics
ID