CT-II

(Q-2(b))
By using the Euler path approach to re-order
the polysilicon lines of the previous chart, we
can obtain an optimum layout.
Find a Euler path in both the pull-down tree
graph and the pull-up tree graph with identical
ordering of the inputs.
Euler path: traverses each branch of the graph
exactly once!
By reordering the input gates as E-D-A-B-C, we
can obtain an optimum layout of the given
CMOS gate with single actives for both NMOS
and PMOS devices (below).

R. W. Knepper
SC571, page 5-
 UNIT III

CMOS Subsystem Design

Schematic and Layout of CMOS
Combinational Circuits:
Full adder circuit,
Multiplexer,
Parity Generator,
Schematic and Layout of CMOS Sequential
Circuits:
SR FlipFlop, JK Flip-Flop, & D Flip-
Flop,
4x4 NOR based ROM Array,
4x4 NAND based ROM Array;
Schematic of SRAM Schematic and
operation of DRAM:
3-T DRAM 6-T SRAM;
 CMOS Full Adder Circuit
Full Adder logic function:

Sum = A XOR B XOR C

= ABC + ABC + ABC + ABC

Carry_out = AB + AC + BC

Sum = ABC + (A + B + C) carry_out

Full Adder Circuit

R. W. Knepper
SC571, page 5-
CMOS - Full Adder Circuit
 CMOS - Full Adder Circuit
This alternate representation of the sum function
allows the full adder to be implemented in complex
CMOS with 28 transistors, as shown below.
Carry_out internal node is used as an input to the
adder complex CMOS gate
 CMOS Full Adder Layout (Complex Logic)

Mask layout of full adder circuit is shown below

A layout designed with Euler method shows that the
carry_out inverter requires separate active shapes, but
all other N (and P) transistors were laid out in a single
active region
Layout below is non-optimized for performance
All transistors are seen to be minimum W/L

R. W. Knepper
SC571, page 5-
CMOS Full Adder Layout (Complex Logic)

R. W. Knepper
SC571, page 5-
Multiplexers

2:1 multiplexer chooses between

two inputs
S
S D1 D0 Y
0 X 0 D0 0
0 X 1
Y
D1 1
1 0 X
1 1 X
Multiplexers

2:1 multiplexer chooses between

two inputs
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1
Gate-Level Mux Design
Y SD1 SD0 (too many transistors)

How many transistors are needed?

Gate-Level Mux Design
Y SD1 SD0 (too many transistors)

How many transistors are needed?

20
D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate Mux

Nonrestoring mux uses two

transmission gates
Transmission Gate Mux

Nonrestoring mux uses two

transmission gates
Only 4 transistors
S

D0
S Y
D1

S
 Inverting Mux

Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an
inverter
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer

4:1 mux chooses one of 4 inputs

using two selects
4:1 Multiplexer

4:1 mux chooses one of 4 inputs

using two selects
Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
Or four tristates

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3
SR Latch Using NOR Gates
Characteristics Table of SR Latch
CMOS SR latch using NOR
Gates
SR Latch Using NAND Gates
CMOS SR latch using NAND
Gates
Clocked RS Flip-Flop
CMOS-Clocked RS Flip-Flop
JK Flip-flop
CMOS JK-Flip-Flop
D-Latch
CMOS implementation of the D-latch
(version 1)
CMOS implementation of the D-latch
(version 2)
 ROM
Read only memories are used to
store constants, control information
and program instructions in digital
systems. They may also be thought
of as components that provide a
fixed, specified binary output for
every binary input.
 ROM
The read only memory can also be seen as a
simple combinational Boolean network, which
produces a specified output value for each
input combination, i.e. for each address. Thus
storing binary information at a particular
address location can be achieved by the
presence or absence of a data path from the
selected row (word line) to the selected
column (bit line), which is equivalent to the
presence or absence of a device at that
particular location.
 ROM
The two different types of
implementations of ROM array are:
NOR-based ROM array
NAND-based ROM array
 NOR based ROM Array
There are two different ways to
implement MOS ROM arrays.
Consider the first 4-bit X 4- bit
memory array as shown in Figure.
Here, each column consists of a
pseudon MOS NOR gate driven by
some of the row signals, i.e., the
word line.
NOR based ROM Array
 NOR based ROM Array
Only one word line is activated at a time by raising voltage to VDD,
while all other rows are held at a low votlage level.

If an active transistor exists at the cross point of a column and the

selected row, the column voltage is pulled down to the logic LOW level
by that transistor.

If no active transistor exists at the cross point, the column voltage is

pulled HIGH by the pMOS load device.

Thus, a logic "1"-bit is stored as the absence of an active transistor,

while a logic "0"-bit is stored as the presence of an active transistor at
the cross point. The truth table is shown in Figure:
NOR based ROM Array
 NAND based ROM Array
In this types of ROM array which is
shown in Figure , each bit line
consists of a depletion-load NAND
gate, driven by some of the row
signals, i.e. the word lines.
 NAND based ROM Array
In normal operation, all word lines are held at the logic HIGH
voltage level except for the selected line, which is pulled down to
logic LOW level.
If a transistor exists at the cross point of a column and the selected
row, that transistor is turned off and column voltage is pulled
HIGH by the load device.
On the other hand, if no transistor exists (shorted) at that particular
cross point, the column voltage is pulled LOW by the other nMOS
transistors in the multi-input NAND structure.
Thus, a logic "1"-bit is stored by the presence of a transistor that
can be deactivated, while a logic "0"-bit is stored by a shorted or
normally ON transistor at the cross point.
NAND based ROM Array
 NAND based ROM Array
As in the NOR ROM case, the NAND-based ROM
array can be fabricated initially with a transistor
connection present at every row-column intersection.
A "0"-bit is then stored by lowering the threshold
voltage of the corresponding nMOS transistor at the
cross point through a channel implant, so that the
transistor remains ON regardless of the gate voltage.
The availability of this process step is also the reason
why depletion-type nMOS load transistors are used
instead of pMOS loads.
NAND based ROM Array
NAND based ROM Array
 RAM Memory Cell
Static RAM
Dynamic Ram
Comparison between Static & Dynamic RAM
Firstly the main difference in the structure varies due
to transistor and capacitor number and setting as just
three to four transistors are required for a Dynamic
RAM, but six to eight MOS transistors are necessary
for a Static RAM.
Secondly Dynamic RAM memory can be deleted and
refreshed while running the program, but in case of
Static RAM it is not possible to refresh programs.
Data is stored as a charge in a capacitor in Dynamic
RAM, where data is stored in flip flop level in Static
RAM.
A Dynamic RAM possesses less space in the chip
than a Static RAM.
 Comparison between Static & Dynamic
RAM
Dynamic RAM is used to create larger RAM space
system, where Static RAM create speed- sensitive cache.
Static ram is 4 times more expensive than Dynamic
RAM.
Dynamic RAM consumes less power than Static RAM.
For accessing a data or information, Static RAM takes
less time than Dynamic RAM.
Dynamic RAM has higher storage capacity. In fact it can
store 4 times than Static RAM.
 3T-DRAM
The three-transistor dynamic RAM structure is
shown in Fig.
Transistor M1 is used to write the BIT logic into
the source of transistor M1 and gate of transistor
M2.
With the present of source capacitance CS,
depending on the logic being written, the gate
voltage of transistor M2 should be either at logic
0 or logic 1 that has voltage (VDD Vtn(M2)).
3T-DRAM
 3T-DRAM
The BIT value is logic 0 then the gate voltage shall be 0V. If
the BIT value is at logic 1 then the gate voltage will be at
logic 1 that has voltage (VWrite Vtn(M2)).
This voltage is hold on as long as the Read transistor M3 is
not switched on.
During the read cycle, transistor M3 is switched on and if
the BIT value is logic 1 then the BIT line would turn logic 0.
Likewise, if the BIT value is logic 0 then upon reading the
BIT line would turn logic 1 that has maximum value (VRead
Vtn(M3)).
Six-Transistor Static Memory
Cell
The six-transistor static memory cell is shown
in Fig. MOS transistor M1, M2, M3, and M4
forms the bi-stable memory element, whilst n-
channel MOS transistor M5 and M6 are served
as pass-transistors.
Six-Transistor Static Memory
Cell
Six-Transistor Static Memory
Cell
During the write cycle, the desired logics are
placed on bit line and BIT line. When the
WORD line is asserted, the desired data will
be latched into the bistable memory element.
For an example, to write logic 1 into the
memory, the BIT line is set at logic 1, whilst
the BIT line is at logic 0.