Pin Diagram of PENTIUM

Microprocessor
Pin Diagram
 CLOCK
CLK - Clock (Input)
Fundamental Timing for the Pentium
The CPU uses this signal as the internal processor clock.
BF - Bus Frequency (Input)
Bus Frequency determines the bus-to-core frequency
ratio
When BF is strapped to Vcc, the processor will operate
at a 2 to 3 bus to core frequency ratio.
When BF is strapped to Vss, the processor will operate
at a 1 to 2 bus to core frequency ratio.
 Initialization
RESET - (Input)
Forces the CPU to begin execution at a known state.
INIT - Initialization (Input)
The Pentium processor initialization input pin forces the
Pentium processor to begin execution in a known state.
The processor state after INIT is the same as the state
after RESET except that the internal caches, write
buffers, and floating point registers retain the values
they had prior to INIT.
 Address Bus
A31:A3 - ADDRESS bus lines
Output except for cache snooping
The number of address lines determines the
amount of memory supported by the processor.
Determines where in the 4GB memory space or
64K IO space the processor is accessing.
These are input lines when AHOLD & EADS# are
active for Inquire Cycles (snooping)
 Address Bus
BE7#:BEO#: Byte Enable lines (Outputs)
Byte Enables to enable each of the 8 bytes in the 64-
bit data path.
Helps define the physical area of memory or I/O accessed.
The Pentium uses Byte Enables to address locations within a
QWORD.
In effect a decode of the address lines A2-A0 which the
Pentium does not generate.
Which lines go active depends on the address, and whether
a byte, word, double word or quad word is required.
 Address Mask
A20M#: Address 20 Mask (Input)
Emulates the address wraparound at 1 MByte which occurs
on the 8086.
When A20M# is asserted, the Pentium processor masks
physical address bit 20 (A20) before performing a lookup to
the internal caches or driving a memory cycle on the bus.
A20#M must be asserted only when the processor is in real
mode.
Internal Parity
IERR# - Internal Error (Output)
Alerts System of Internal Parity Errors
 Address Parity
AP Address Parity (I/O)
Bi-directional address parity pin for the address lines.
Address Parity is driven by the Pentium processor with even
parity information on all CPU generated cycles in the same
clock that the address is driven
Even parity must be driven back to the CPU during inquire
cycles on this pin in the same clock as EADS#.
Not supported on all systems
APCHK#: Address Parity Check Signal (Output)
The status of the address parity check is driven on the
APCHK# output.
Even Parity Checking
 Data Bus.
D63:DO - Data Lines (I/O).
The bi-directional 64-bit data path to or from the CPU.
The signal W/R# distinguishes direction.
During reads, the CPU samples the data bus when
BRDY# is asserted.
DP7: DP0 - Data Parity (I/O)
Bi-directional data parity pins for the data bus.
Even Parity Check. One for each byte of the data bus
Output on writes, Input on reads.
Not supported on all systems.
 Bus Control
ADS# - Address Strobe (output)
Indicates that a new valid bus cycle is currently being
driven by the Pentium processor.
The following are some of the signals which are valid
when ADS#=0
Addresses (A31:3)
Byte Enables (BE7#:0#)
Bus Cycle definition (M/IO#; D/C#; W/R#, CACHE#)
From power-on the ADS# signal should be asserted
periodically when bus cycles are running
 Bus Control (Cont.)
BRDY# - Burst Ready (Input)
Transfer complete indication.
The burst ready input indicates that the external system
has presented data on the data pins in response to a
read or that the external system has accepted the
Pentium processor data in response to a write request.
This signal ends the current bus cycle and is used to
extend bus cycles to allow slow devices extra time.
If LOW (non-burst cycles), this signal ends the current
bus cycle and the next bus cycle can begin.
If HIGH the Pentium is prevented from continuing
processing and wait states are added.
 Bus Cycle Definition
M/IO# - Memory or Input/Output (output)
M/IO# distinguishes between Memory and I/O cycles.
The memory/input-output is one of the primary bus
cycle definition pins.
1 = Memory Cycle
0 = Input/Output Cycle
It is driven valid in the same clock as the ADS# signal is
asserted.
 Bus Cycle Definition (Cont.)
D/C# - Data or Code (output)
D/C# distinguishes between data and code or special
cycles (control)
The data/code output is one of the primary bus cycle
definition pins.
1 = Data
0 = Code / Control
Control for Interrupt Acknowledge or Special Cycles
It is driven valid in the same clock as the ADS# signal is
asserted.
 Bus Cycle Definition (Cont.)
W/R# - Write or Read (output)
W/R# distinguishes between Write and Read cycles.
Write/read is one of the primary bus cycle definition
pins.
1 = Write
0 = Read
It is driven valid in the same clock as the ADS# signal
is asserted.
 Bus Cycle Definition (Cont.)
Cache# - Cache ability (output)
Processor indication of internal cache ability.
The L1 cache must be enabled using the CD bit in CR0
for Cache# to be asserted low.
The Cache# signal could also be described as the BURST
instruction signal, because the Cache# signal (qualified
with KEN#) results in a burst mode transfer of 32 bytes
of code or data.
Cache# and Ken# are used together to determine if a
read will be turned into a linefill. (Burst cycle).
During write-back cycles, the CPU asserts the CACHE#
signal (KEN# does not have to be asserted)
 Bus Cycle Definition (Cont.)
NA# - Next Address (Input)
Indicates external memory is prepared for a pipeline
cycle.
An active next address input indicates that the external
memory system is ready to accept a new bus cycle
although all data transfers for the current cycle have
not yet completed.
When NA# is asserted, the Pentium supplies the
address for the start of the next transfer early, so that
the memory system can latch the new address before
the transfer is ready to start.
A detailed discussion of Address Pipelining is beyond
the scope of this course.
 Bus Cycle Definition (Cont.)
Lock# - Bus Lock (Output)
The bus lock pin indicates that the current bus cycle is
locked, typically for a read-modify-write operation.
The CPU will not allow a bus hold when LOCK# is
asserted.
Locked cycles are generated when the programmer
prefixes certain instructions with the LOCK prefix.
e.g. LOCK INC [EDI] ;Increment a memory location
Locked cycles are generated automatically for certain
bus transfer operations.
Interrupt Acknowledge cycles
The XCHG instructions when 1 operand is memory-based.
See Pentium manual for more details.
 Cache Control
KEN# - Cache Enable (Input)
Indicates to the Pentium whether or not the system can
support a cache line fill for the current cycle.
Cache# and Ken# are used together to determine if a
read will be turned into a linefill. (Burst cycle).
WB/WT# - Write-back/Write-through (Input)
This pin allows a cache line to be defined as a a write
back or write-through on a line by line basis.
 Bus Arbitration
HOLD - Bus Hold (Input)
Allows another bus master complete control of the CPU
bus.
In response to the bus hold request, the Pentium
processor will float most of its output and input/output
pins and assert HLDA after completing all outstanding
bus cycles.
The Pentium processor will maintain its bus in this state
until HOLD is de-asserted.
HLDA - Bus Hold Acknowledge (Output)
External indication that the Pentium outputs are
floated.
 Bus Arbitration (Cont.)
BOFF# - Backoff (Input)
Forces the Pentium to get off the bus in the next clock.
After BOFF# is removed, the Pentium restarts the bus
cycle.
BREQ - Bus Request (output)
Indicates externally when a bus cycle is pending
internally.
Used to inform the arbitration logic that the Pentium
need control of the bus to perform a bus cycle.
 Interrupts
INTR - Maskable Interrupt (Input)
Indicates that an external interrupt has been generated.
If the IF(Interrupt Enable Flag) bit in the EFLAGS register is
set, the Pentium processor will generate two locked
interrupt acknowledge bus cycles (to get type number) and
vectors to an interrupt handler after the current instruction
execution is completed.
NMI - Non-Maskable Interrupt (Input)
Indicates that an external non maskable interrupt has been
generated.
The Pentium processor will vector to a Type 2 interrupt
handler after the current instruction execution is completed
 Probe Mode
R/S# - Resume/Stop [Run/Scan] (Input)
The run/stop input is an asynchronous, edge-sensitive
interrupt used to stop the normal execution of the
processor and place it into an idle state.
PRDY - Probe Ready (Output)
The probe ready output pin indicates that the
processor has stopped normal execution in response to
the R/S# pin going active. The CPU enters Probe Mode.