ECE 3110: Introduction to Digital Systems

Chapter 6
Combinational Logic Design Practices

Adders, subtractors,
ALUs
Prev

XOR (2-level, 3-level)

Equivalent symbols
XNOR
Parity Circuits (Odd, even)
Daisy chain
Tree
Comparators
Iterative
Parallel
Adders/Subtractors
Half Adder
Full Adder
Ripple Adder

Full Subtractor
Ripple Subtractor
Adder/ Subtractor Circuit
Half Adder: adds two 1-bit operands

Truth table :

X Y HS=(X+Y) CO X
0 0 0 0 HS
Y
0 1 1 0
1 0 1 0 CO
1 1 0 1

HS X Y
CO X Y
 Full Adders: provide for carries
between bit positions
Basic building block is full adder
1-bit-wide adder, produces sum and carry outputs
Truth table:
 Full Adders: provide for carries
between bit positions
Basic building block is full adder
1-bit-wide adder, produces sum and carry outputs
Truth table:
X Y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full Adders: provide for carries
between bit positions
Basic building block is full adder
1-bit-wide adder, produces sum and carry outputs
Truth table:
X Y Cin S Cout
S is 1 if an odd number 0 0 0 0 0
of inputs are 1. 0 0 1 1 0
0 1 0 1 0
COUT is 1 if two or 0 1 1 0 1
more of the inputs are 1 0 0 1 0
1. 1 0 1 0 1
Recall: Table 2-3, pp32 1 1 0 0 1
1 1 1 1 1
Full-adder circuit
Full-adder circuit
Full-adder circuit
 Ripple adder

Speed limited by carry chain

Faster adders eliminate or limit carry chain
2-level AND-OR logic ==> 2n product terms
3 or 4 levels of logic, carry look-ahead
 74x283
4-bit adder

Uses carry
look-ahead
internally
16-bit
group-ripple
adder
Subtraction

Subtraction is the same as addition of the

twos complement.
The twos complement is the bit-by-bit
complement plus 1.
Therefore, X Y = X + Y + 1
Full Subtractor = full adder, almost

X,Y are n-bit unsigned binary numbers

Addition : S=X+Y
Subtraction : D = X - Y = X + (-Y) =
= X+ (Twos Complement of Y)
= X+ (Ones Complement of Y) + 1
= X+ Y+ 1
Full Subtractor = full adder, almost

X,Y are n-bit unsigned binary numbers

Addition : S=X+Y
Subtraction : D = X - Y = X + (-Y) =
= X+ (Twos Complement of Y)
= X+ (Ones Complement of Y) + 1
= X+ Y+ 1
Using Adder as a Subtractor

Ripple Adder can be used as a Subtractor by inverting Y and setting the

initial carry ( CIN ) to 1
Using Adder as a Subtractor

Ripple Adder can be used as a Subtractor by inverting Y and setting the

initial carry ( CIN ) to 1
 MSI Arithmetic Logic Units (ALU )
74x181
ALU performs Arithmetic and Logical Functions
S0
- A , B : 4 bits inputs
- S3,S2,S1,S0 : Function select S1
G
- M=0 : Arithmetic operations +=Plus , - = Minus S2
M=1 : Logical operations : += OR , . =AND S3 P

Example : M A=B
Inputs Functions CIN
S3 S2 S1 S0 M=0 M=1 A0 F0
0 0 0 0 F= A-1+CIN F=A B0 F1
0 1 1 0 F= A-B-1+CIN F=A XOR B A1 F2
1 0 0 1 F= A+B+CIN F=A XOR B B1 F3
1 0 1 1 F=(A OR B)+ CIN F=A+B
A2
1 1 0 0 F= A+A+CIN F= 0000 COUT
B2
1 1 1 1 F=A+CIN F=A
A3
B3
Chapter Summary

Documentation Standards:
- Gate symbols, Signals Active Levels, Bubble to Bubble Logic
- Block diagram, Schematic Diagram, Timing Diagram.
Combinational Logic design Structures:
1-Decoders :
Binary Decoders, Cascading decoders
2-Encoders :
Binary Encoder, Priority Encoder, Cascading Encoders,
Encoder applications.
3-Three State Buffers :
SSI buffers, MSI Octal Buffer , Octal Three-state Transceiver
Chapter Summary

4- Multiplexers :
MUX operation, Single/Multiple outputs MUX, Expanding
MUXs
5- Demultiplexers :
MUX/DMUX operation, Using Decoders as Demultiplexers.
6- XOR and XNOR Gates:
Logic Symbols, Equivalent Symbols, Parity Circuits, Parity
Circuit application ( memory unit checking )
7- Comparators :
Parallel Comparators, Iterative Comparators, Cascading
Comparators
8-Adders :
Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder /
Subtractor Unit,
9- Arithmetic Logic Units
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