1

Bus Interconnection
1. Bus is communication path between two or more components
2. Shared Transmission Medium
3. Signal Tx by One Device is available to Rx by all the other Devices
attached to bus.
4. Only one can successfully transmit at one point of time.
5. It consists of Multiple communication pathways (Lines - Serial and
Parallel).
6. Bus Connecting Major Components Like CPU, Memory and I/O is
called as System Bus.
Bus Interconnection Scheme

3
 Bus Structure
1. Bus consists of 50-100 Separate Lines.
2. Data,Address, Control Lines.
3. Data Lines:- : Provides path for moving Data between Devices
(8,16,32,Bits).
4. Address Lines:- Used to Designate Source or Destination of the
data in data bus.
5. Control Lines:- Used to Control data and address lines. Transmits
both commands and timings information between modules.
Memory Write, Memory Read, I/0 Write, I/0 Read, Transfer Ack, Bus
Request, Bus Grant, Interrupt Request, Interrupt Ack, Clock and
Reset.
Multiple Bus Hierarchy
High Performance Architecture
Element Of Bus Design
 Slip Test 1
5 Questions X 5 Marks = Total 25 Marks
1. Brief Description of Computer Evolution?
2. Define Bus, Bus Structure and Different types of Bus,
Elements of Bus Design?
3. Explain Multiplexer, 4-Bit Shift Register Draw its
Truth Table?
4. Draw S-R, D, J-K, J-K Master Slave and T Flip Flop and
Explain it with Truth Table?
5. Convert the Given number (999)10 in to Binary, Octal
and Hexa Decimal number?
 Evolution of INTEL Micro Processor

Intel first manufactured 4004 4-Bit Micro Processor.

2000 Transistors, 46Instructions, 4kb Program Code and 1kb data.
Second Generation
Intel Manufactured 8 bit Micro Processors (8008,8080 and 8085).
Third Generation 16 bit Micro Processors
8086 16 Bit micro processor
IBM Realized the processing speed and included it in IBM PC.
Intel 8086 Micro Processor Architecture
 Intel 8086 Micro Processor Architecture

8086 Micro Processor is a 16-bit Microprocessor .

8086 having 20 address lines and 16 data lines that
provides up to 1MB storage.
BIU (Bus Interface Unit) contains 16 Bit Segment Registers.
Code Segment, Data Segment, Stack Segment and Extra
Segment.
Flags:- Carry, Auxiliary, Parity, Zero, Sign, Over Flow, Trap,
Interrupt and Direction flag.
General Purpose Registers:- AH, AL, BH, BL, CH, CL, DH, DL
individually and as a pair AX,BX, CX and DX.
Register Transfer language
&
Microoperations
 Register Transfer and Micro operations
The Operations Executed on the data stored in register are
called Micro Operations.
The Result of the operation may replace the previous binary
information of a register or may be to transferred to another
register.
Examples :- Shift, Count, Clear and Load. Counter with parallel
Load, Bi Directional Shift Registers.
Internal Hardware Organization Of a Digital
computer Defined By:-

The Set of Registers contained and their function.

The Sequence of Micro Operations performed on binary
information stored in Registers.
Control that initiates the sequence of Microoperations.
 Register Transfer Language
The Symbolic notation used to describe the micro operation transfers among
registers is called Register Transfer Language.
Register : - Computer Registers are designated by Capital Letters(Some
times followed by Numerical) Ex:- MAR(Memory Address Register),
PC(Program Counter), IR(Instruction Register).
Register Transfer:- Information Transfer from One register to other Register
is designated in Symbolic Form by means of replacement operator.
Ex:- R2 R1.
Control Function: Boolean variable that is equal to 1 or 0. P : R2 R1.

Block Diagram Timing Diagram

Basic Symbols for Register Transfer

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow Denotes transfer of information R2 R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A B, B A
Bus System for four Registers
Bus Line with Three State Buffers
MEMORY TRANSFER
Memory Read :- Transfer of information from a memory to the outside
environment is called Read Operation. Read: DR M [AR]

Memory Write :- Transfer of New information to be stored in to memory is

called Write Operation. Write: M [AR] R1

Read
Memory
AR unit

Write

Data out Data in

MICROOPERATIONS

1. Register transfer micro operations:- Transfers Binary information from

one register to another.

2. Arithmetic micro operations:- Performs Arithmetic operations on

Numeric Data Stored in Registers.

3. Logic micro operations:- Performs Bit Manipulation Operations on

Numeric Data Stored In Registers.

4. Shift micro operations:- Performs Shift Operations on Data Stored in

Registers.
ARITHMETIC MICROOPERATIONS

Symbol Description
Contents of R1 plus R2 transferred to R3
R3 R1 + R2
Contents of R1 minus R2 transferred to R3
R3 R1 - R2
R2 R2 Complement the contents of R2
R3 R1 + R2+ 1
2's complement the contents of R2 (negative)

R2 R2+ 1 2s Complement

R1 R1 + 1 Increment

R1 R1 1 Decrement
BINARY ADDER / SUBTRACTOR /
INCREMENTER

Binary Adder

Binary Adder-Subtractor

A3 A2 A1 A0 1

x y x y x y x y
Binary Incrementer HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0
4 Bit Arithmetic Circuit
Arithmetic Table Function Table

S1 S0 Cin Y Output Microoperation

0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B D = A + B Subtract with borrow
0 1 1 B D = A + B+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
 Slip Test 2 5 Questions X 5 Marks = Total 25 Marks

1)Design Bus System for four Registers ?

2)Design Bus Line With three State Buffer?
3)Define Register Transfer Language and Micro
Operations ?
4)List Different Types of Arithmetic Micro
Operations, Design and Explain Arithmetic circuit?
5)Block Diagram of 8086 Micro Processor?
 Logical Micro Operations
Boolean Function Micro Operation Name
F=0 f- 0 Clear
F = xy FAB AND
F2 = xy' F A B

F3 = x FA Transfer A
F4 = x'y F A B

F5 = y FB Transfer B
F6 = x y FAB Exclusive-OR

F7 = x + y FAB OR

F8 = (x + y)' F A B) NOR

F9 = (x y)' F (A B) Exclusive-NOR

F10 = y' F B Complement B

F11 = x + y' FAB

F12 = x' F A Complement A

F13 = x' + y F A B

F14 = (xy)' F (A B) NAND

F15 = 1 F all 1's Set to all 1's

 Logic Micro Operations
Hardware Implementation

S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A Complement
 Logic micro operations can be used to manipulate individual bits or a
portions of a word in a register

Consider the data in a register A. In another register, B, is bit data

that will be used to modify the contents of A
Selective-set AA+B
Selective-complement AAB
Selective-clear A A B
Mask (Delete) AAB
Clear AAB
Insert A (A B) + C
Compare AAB
 SELECTIVE SET

In a selective set operation, the bit pattern in B is used to

set certain bits in A

1100 At
1010 B
1110 At+1 (A A + B)
If a bit in B is set to 1, that same position in A gets set to 1,
otherwise that bit in A keeps its previous value
 SELECTIVE COMPLEMENT

In a selective complement operation, the bit pattern in B is used to

complement certain bits in A
1100 At
1010 B
0110 At+1 (A A B)

If a bit in B is set to 1, that same position in A gets complemented

from its original value, otherwise it is unchanged
 SELECTIVE CLEAR

In a selective clear operation, the bit pattern in B is used to

clear certain bits in A

1100 At
1010 B
0100 At+1 (A A B)

If a bit in B is set to 1, that same position in A gets set to 0,

otherwise it is unchanged
 MASK OPERATION
In a mask operation, the bit pattern in B is used to clear
certain bits in A

1100 At
1010 B
1000 At+1 (A A B)

If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged
 CLEAR OPERATION
In a clear operation, if the bits in the same position in A and
B are the same, they are cleared in A, otherwise they are
set in A.
1100 At
1010 B
0110 At+1 (A A B)
 INSERT OPERATION
An insert operation is used to introduce a specific bit pattern into A register, leaving the
other bit positions unchanged

This is done as A mask operation to clear the desired bit positions, followed by

An OR operation to introduce the new bits into the desired positions

Suppose you wanted to introduce 1010 into the low order four bits of
A:1101 1000 1011 0001 A (Original) 1101 1000 1011 1010 A (Desired)

1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask ( A.B)
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits (A+B)
1101 1000 1011 1010 A (Desired)
 SHIFT MICROOPERATIONS
There are three types of shifts

Logical shift

Circular shift

Arithmetic shift

What differentiates them is the information that goes into the serial input

Serial
input

Serial
input
 LOGICAL SHIFT
In a logical shift the serial input to the shift is a 0.
A right logical shift operation:

A left logical shift operation:

0

In a Register Transfer Language, the following notation is used

shl for a logical shift left
shr for a logical shift right
Examples:
R2 shr R2
R3 shl R3
 CIRCULAR SHIFT
In a circular shift the serial input is the bit that is shifted out of the other end of
the register.
A right circular shift operation:

A left circular shift operation:

In a RTL, the following notation is used

cil for a circular shift left
cir for a circular shift right
Examples:
R2 cir R2
R3 cil R3
 ARITHMETIC SHIFT
An arithmetic shift is meant for signed binary numbers (integer)

An arithmetic left shift Multiplies a signed number by two

An arithmetic right shift Divides a signed number by two

The main distinction of an arithmetic shift is that it must keep the sign of
the number the same as it performs the multiplication or division
sign
bit

A right arithmetic shift operation:

0
sign
bit

A left arithmetic shift operation:

 ARITHMETIC SHIFT
An left arithmetic shift operation must be checked for the Overflow

0
sign
bit

Before the shift, if the leftmost two bits differ, the shift will result in an
overflow

In a RTL, the following notation is used

ashl for an arithmetic shift left
ashr for an arithmetic shift right
Examples:
R2 ashr R2
R3 ashl R3
HARDWARE IMPLEMENTATION OF SHIFT
MICROOPERATIONS

0 for shift right (down)

Serial Select 1 for shift left (up)
input (IR)

S
MUX H0
0
1
A0
A1 S
MUX H1
0
A2 1

A3
S
MUX H2
0
1

S
MUX H3
0
1

Serial
input (IL) Select Line H0 H1 H2 H3
0 IR A0 A1 A2
1 A1 A2 A3 IL
 ARITHMETIC LOGIC SHIFT UNIT

S3
S2 C
i
S1
S0

D
Arithmetic i

Circuit
Select

0 4x1 F
C i+1 i
1 MUX
2
3

E
Logic i
B
i Circuit
A
i
shr
A
i-1
shl
A
i+1
 Unit II
Basic Computer
Organization and Design
 BASIC COMPUTER ORGANIZATION AND
DESIGN
Instruction Codes
Computer Registers
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference instructions
Input-Output and Interrupt
Central Processing Unit
Stack Instruction Formats
Addressing modes
Data Transfer and Manipulations
Program and RISC
 INSTRUCTION CODES
1. Organization of computer is defined by its Internal Registers, Timing
and Control structure and Instructions that it uses.
2. Internal Organization of a digital system is defined by Sequence of
micro operations it performs on data stored in registers.
3. User of a computer can control the process by means of a program.
4. Program is a set of Instructions that specify the operations, operands,
and Sequence by which it Operates.
5. Computer Instruction is a Binary Code that Specifies a Sequence of
Micro Operations for the computer.
6. Instruction Code is group of bits the instructs the computer to perform
a specific operation.
 INSTRUCTION CODES
Operation code of a Instruction is a group of bits that define operations
such as ADD, Subtract, Multiply, Shift, and complement.
No of Bits depends of no of operations performed by computer.
 STORED PROGRAM ORGANIZATION
One Processor Register and an Instruction Code format with two parts,
First Part is Opcode and Second Specifies Address.
Memory Address tells the control where to find an operand in Memory.
The Operand is read from memory and used as data to be operated on
together with data stored in Processor Register.
 ACCUMULATOR
Computers that have Single Processor Register usually assign to
Accumulator (AC).

The Operation is performed with the Memory Operand and Content of AC.

If an operation in Instruction code does not need a Operand from memory,

The rest of the bits can be used for other purpose.

EX: Clear AC, Complement AC, Increment & Decrement AC which

operated on data stored in AC.

For the above operation the bits from 0-11 is not needed for specifying a
memory address, It can be used to specify other operations for the
computer.
ADDRESSING MODES
COMPUTER REGISTERS
COMPUTER REGISTERS
COMMON BUS SYSTEM
 COMMON BUS SYSTEM
Computer will have 8 Registers, Memory Unit and a Control unit.

Paths must be Provided to transfer information from one register to another

and between memory and register.

Efficient way is to use Bus system to transfer information in a system with

many registers. The outputs of seven registers are connected to Bus System.

Load is Enabled receives data from bus during the next clock transaction.

Write is Enabled Memory receives contents of the bus.

Read input is Enabled Memory places 16 bit output on to the Bus.

LD, INR, CLR registers equivalent to a binary counter with parallel load.
 COMMON BUS SYSTEM
16 Inputs of Accumulator come from an Adder and Logic Circuit, Circuit
has 3 sets of inputs.
1. Output of Accumulator Ex. Complement, Shift.
2. Data Register (DR) Ex. Arithmetic and Logical Micro Operations.
3. INPR.

Input Register INPR and Output Register OUTR have 8 bits each and
communicate with the LSB 8 bits of BUS.

INPR is connected to Provide data to bus.

OUTR can only Receive information from bus.

 COMPUTER INSTRUCTIONS
Basic computer will have 3 Instruction Code formats with 16 bits, Opcode
will have 3 bits and remaining 13 depends on operation.

Memory Reference Instructions:- 12 bits to Specify Address, 1 Bit

Addressing Mode, 0- Direct and 1- Indirect.

Register Reference Instructions:- Opcode-111 and 0- Left Most bit.

Operation on Accumulator Register. Operand from memory is not needed.

Input-Output Instructions:- Opcode-111 and 1- Left Most bit, 12 Bits

Specify Input, Output Operation to be performed.

3 bits used for the Operation Code. Computer is restricted to 8 Different

Operations. Since Register Reference and Input / Output Instructions uses
12 bits as part of Opcode. We can Assign 25 Instructions.
COMPUTER INSTRUCTIONS
Memory Reference Instructions

Register Reference Instructions

Input-Output Instructions
 INSTRUCTION SET COMPLETENESS
Type of instructions that should be included in a computer.

A Computer should have a set of instructions so that user can construct

Machine language Programs to evaluate any function that is know to be
computable.
1. Arithmetic, Logical and Shift Instructions.
2. Instructions for moving information to and from memory and
processor registers.
3. Program control instructions together with instructions that check
status conditions.
4. Input and output instructions.
 TIMING AND CONTROL
Clock Pulses are applied to all Flip-Flops and Registers in the
System.
Clock Pulses does not change the state of Register unless the
Register is Enabled by a Control Signal.
Control Signals are generated in Control Unit
Control Inputs for Multiplexers in the common bus, control
input in Processor register, Micro Operations from registers.
 Timing and Control
Hardwired Control & Micro Programmed Control
Two Types of Control Organization: Hardwired Control and
Micro Programmed Control
Hardwired Control:- Control Implemented with Gates, Flip-
Flops, Decoders, and other digital Circuits. Optimized for Fast
mode of Operation.
Wiring among the various components.
Micro Programmed Control:- Control Information is stored in
Control memory , Control is programmed to initiate required
sequence of micro operations.
Control Unit Of Basic Computer
 CONTROL UNIT

Two Decoders and one Sequence Counter & Control Logic Gates
Instruction read from memory is place in IR(I, OPCODE, ADDRESS).
OPCODE:- Decoded With 3x8 Decoder, Eight Outputs D0-D7.
I- It is given to Flip Flop.
Bit 0-11 are applied to Control Logic.
4-bit Sequence Counter Can count from 0-15 . Outputs of the
Counter are Decoded in to 16 Timing Signals T0-T15.
TIMING SIGNALS
 INSTRUCTION CYCLE

Fetch an Instruction from Memory.

Decode the instruction.

Read the Effective address from Memory if the instruction has an

Indirect address.

Execute the Instruction.

REGISTER TRANSFER FOR THE FETCH PHASE

T0: PC AR

T1: IR M[AR], PC PC + 1

T2: D7-D0 DECODE (IR(12-14)),

I IR(15), AR IR(0-11)
 INSTRUCTION CYCLE

1) Place the content of PC onto the bus by making the bus selection
inputs S2S1S0 equal to 010.
2) Transfer the content of the bus to AR by enabling the LD input of
AR.
3) The Next clock transition initiates the transfer from PC to AR since
T0=1, In order to implement the second statement.
T1 : IR M[AR], PC PC + 1
 Timing Signal T1

1) Enable Read Input of Memory

2) Place the content of Memory on to the bus by making S2S1S0 =
111.
3) Transfer the content of the bus to IR by enabling LD input of IR.
4) Increment PC by enabling the INR input of PC.
FLOW CHART FOR INSTRUCTION CYCLE
1) Time T3 the control unit determines the type of instruction that
was just read from Memory.
2) D7 = 1 if the operation code is equal to binary 111.
3) D7=1 instruction must be Register Reference or Input-Output
Type.
4) D7=0 the Operation code must be 000 to 110, Specifying a
Memory Reference Instruction.
5) I=0 Direct, I=1 Indirect.
 Indirect Address
ARM[AR].

The Micro Operation for the indirect address condition can be

symbolized by the register transfer statement.

AR Holds address part of the instruction. The address is used

during the method read operation.

D~7IT3 : AR M[AR]

D~7IT3 : Nothing

D7I~T3 : Execute a Register-Reference Register

D7IT3 : Execute an Input-Output Instructions.

REGISTER REFERENCE INSTRUCTIONS
MEMORY REFERENCE INSTRUCTIONS
 MEMORY REFERENE INSTRUCTIONS

AND to AC
D0T4 : DR M[AR]
D0T5: AC AC DR
ADD to AC
D1T4: DRM[AR]
D1T3: ACAC + DR, E Cout SC0
LDA: Load to AC
D2T4: DRM[AR]
D2T5: ACDR, SC 0
STA: Store AC
D3T4: M[AR] AC, SC0
INPUT-OUTPUT AND INTERUPPT
INPUT-OUTPUT INSTRUCTIONS
INPUT-OUTPUT AND INTERUPPT
 Central Processing Unit
1. Part of Computer that Perform Bulk data procession operations is called
Central Procession Unit.
2. CPU is made of three Units 1)Register Set 2) ALU 3) Control Unit
3. Instruction formats, Addressing modes, Instruction set.
4. General Organization of the CPU registers leading to two architectures RISC
(Reduced Instruction Set Computer) CISC (Complex Instruction Set Computer)
5. Based on Memory Usage for data and programs it is of two types embedded
(Harvard Computer Architecture) and non embedded (SPC).
 General Register Organization
Input
Clock

R1

R2

R3

R4
Binary
R5
Code SELA SELB SELD
R6
000 Input Input None
001 R1 R1 R1
R7
010 R2 R2 R2
Load
(7 lines)
011 R3 R3 R3
{ } 100 R4 R4 R4
SELA
MUX MUX SELB
101 R5 R5 R5
110 R6 R6 R6
3x8
decoder
A bus B bus 111 R7 R7 R7

SELD
OPR ALU

Output
 ALU CONTROL
OPR
Encoding of ALU operations Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
Control Word 00101 Subtract A - B SUB
00110 Decrement A DECA
3 3 3 5
01000 AND A and B AND
SELA SELB SELD OPR 01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Micro operations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1 R2 R3 R2 R3 R1 SUB 010 011 001 00101
R4 R4 R5 R4 R5 R4 OR 100 101 100 01010
R6 R6 + 1 R6 - R6 INCA 110 000 110 00001
R7 R1 R1 - R7 TSFA 001 000 111 00000
Output R2 R2 - None TSFA 010 000 000 00000
Output Input Input - None TSFA 000 000 000 00000
R4 shl R4 R4 - R4 SHLA 100 000 100 11000
R5 0 R5 R5 R5 XOR 101 101 101 01100
 STACK ORGANIZATION
Stack (LAST IN FIRST OUT)
Stack Pointer:- Register that holds the address of stack is called
stack pointer. Its value always points at the top item in the stack.
Two operations are Insert and Delete, Operation of insertion is
PUSH, Operation of Deletion is called POP.
Stack Address
63
Flags

FULL EMPTY

Stack pointer
4
SP C 3
6 bits B 2

A 1

DR
 STACK ORGANIZATION
Push
Stack Address
63
SP SP+1
Flags
M[SP] DR
FULL EMPTY If (SP = 0) Then (FULL 1)
EMTY 0

Stack Pointer 4

SP 3
POP
C
6 bits B
2 DR M[SP]
SP SP-1
1
A
0

If (SP=0) Then (EMTY 1)

DR FULL 0
 Computer Memory

PC Program
(instructions)

AR Data
(operands)

3000
SP
stack
3997
3998
3999
4000
4001
 REVERSE POLISH NOTATION
Arithmetic Expressions: A + B
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation

Evaluation of Arithmetic Expressions

Any arithmetic expression can be expressed in parenthesis-free Polish
notation, including reverse Polish notation.

(3 * 4) + (5 * 6) 34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
 INSTRUCTION FORMATS
An Operation Code field that specifies the operation to be
performed.(ADD, SUB, Complement and Shift)
An Address Field that designates a memory address or a processor
register.
A mode field that specifies the way the operand or the effective address
is determined.
Single Accumulator Organization (Operations Implied on AC register)
ADD X AC AC + M[X]

General Register Organization. Stack Organization PUSH x, ADD

ADD R1,R2, R3 R1 R2 + R3
ADD R1, R2 R1 R1+R2
MOV R1,R2 R1 R2
ADD R1,X R1 R1 + M[X]
 INSTRUCTION FORMATS

X = (A + B) * (C + D)
Three Address Instructions
ADD R1, A, B R1 M[A] + M[B]
ADD R2, C, D R2 M[C] + M[D]
MUL X,R1,R2 M[X] R1 * R2
Two Address Instructions
MOV R1, A R1 M[A]
ADD R1, B R1 R1 + M[B]
MOV R2, C R2 M[C]
ADD R2, D R2 R2 + M[D]
MUL R1,R2 R1 R1 * R2
MOV X, R1 M[X] R1
 DATA TRANSFER AND DATA MANIPULATION
Most Computer Instructions are classified in to three

1. Data Transfer Instructions

2. Data Manipulation

3. Program Control

Data Transfer Instructions: Transfer of data from one location to another

location without changing the binary information content.

Data Manipulation:- Perform Arithmetic, Logical and Shift operations.

Data Transfer Instructions Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data Manipulation Instructions
 ADDRESSING MODES
1. Immediate Mode

2. Register Mode

3. Register Indirect Mode

4. Auto Increment or Auto Decrement Mode

5. Direct Addressing Mode

6. Indirect Addressing Mode

7. Relative Address Mode

8. Indexed Addressing Mode

9. Base Register Addressing Mode

 ADDRESSING MODES
Immediate Mode :-
In this mode the operand is specified in the instruction itself, It has operand field
rather than address field.
Used for initializing registers to a constant value.

Register Mode:- Operand specifies CPU Registers

Register Indirect Mode :- Specifies a register in CPU, Whose contents give the
address of operand in memory.
Advantage in indirect mode is that the address field of the instruction uses fewer
bits to select register.

Auto Increment or Auto Decrement Mode:- Similar to register indirect mode that
the register is incremented or decremented after or before its value is used to
access the memory.
Register refers to a table of data in memory.
 ADDRESSING MODES
Effective Address:- It is used by the control unit in the CPU to obtain the
operand from memory.

Effective Address = Address part of Instruction + Content of CPU

Address of the operand in a computational type instruction.

It is the address where control branches in response to a branch type

instruction.

Direct Address Mode:- In this mode the effective address is equal to the
address of instruction. Address is given directly by the address field of the
instruction

Indirect Address Mode:- Address field of the instruction gives the address
where effective address is stored in memory.
 ADDRESSING MODES
Relative Addressing Mode :- In this mode Contents of PC added to
Address part of Instruction in order to obtain Effective Address.

It is often used in branch type instructions, When branch address is in

area surrounding the instruction word.

Indexed Addressing Mode:- In this Mode content of Indexed Register is

added to the address part of the instruction to obtain effective address.

Base Register Addressing Mode:- In this Mode content of base register is

added to the address part of the instruction.

Used When data and program are moved from one Segment of memory
to another
Memory Organization
Memory Hierarchy
MEMORY:- It is used to store program and data.

Main Memory:- The memory that communicates directly with the CPU is
called Main Memory.

Programs and Data Currently needed by the processor.

Auxiliary Memory:- The memory that provides back up Storage are called
Auxiliary Memory. Examples:- Magnetic Disks and Tapes.

They are used for storing system programs, Large Files, and other
backup information.

Cache Memory:- Very High Speed Memory called cache used to increase
the speed of processing by making current programs and data available to
CPU at a rapid rate.
1. Main Memory is based on Semi Conductor Integrated Circuits.

2. Integrated Circuits RAM chips are available in two possible

operating Modes Static and Dynamic.

3. Static RAM Consists essentially of internal Flip Flops that

Stores the binary information as long as power is applied to
unit.

4. Dynamic RAM Stores information in the form of electric

charges that are applied to capacitor.

5. BootStrap:- ROM portion of main memory is needed for

storing an initial program called bootstrap loader.
 RAM

Typical RAM Chip

 RAM
1. One or More control inputs that select the chip only when needed.
2. Bidirectional data Bus that allows transfer of data either from memory
to CPU(Read Operation) or CPU to Memory(Write Operation).
3. Bidirectional data bus is Constructed using 3 State Buffers. Buffer output
can be three states, Signal equivalent to logic-1, Signal Equivalent to
Logic 0 or high Impudence.
4. Capacity of Memory is 128 Words of Eight Bits (One byte) per word.
5. 7 Bit address and a 8 bit bi-directional bus.
6. Read and Write Specifies the memory operation.
7. Chip Select for enabling the chip only when it is selected by
microprocessor.
 ROM

Memory Mapping
Address Space Assignment to each memory chip.
 Memory Connection to CPU
1. RAM and ROM chips are connected to a CPU through the data and
address buses.
2. Lower Order lines in the address bus select the byte with in the chips
and other lines in the address bus selects particular chip through chip
selection.
3. 7-Lower Bits used to select one of the 128 Possible Bytes.
4. 8-9 Lines in the address bus to select the RAM.
5. Selection Between RAM and ROM is achieved through bus line 10.
6. The RAMs are Selected when the bit in this line is 0, ROM when bit is 1.
7. Address Lines 1-9 are applied to the input address of ROM without
going through the decoder.
8. Data bus of ROM has only an output Capability, Where as data bus
connected to the RAMs can transfer information in both directions.
Memory Connection to CPU
 Auxiliary Memory
Most common memory device used in computer Systems are magnetic
disks and tapes.

Important Characteristics of any device are its Access mode, Access time,
Transfer rate, Capacity and Cost.

The average time required to reach a storage location in memory and

obtain its contains is called access time.

Electro Mechanical Devices with moving parts such as disks and tapes,
The access time consists of a Seek time required to position the read and
read-write head to a location.

Transfer time required to Transfer data to or from the device.

High speed Rotation surface coated with a Magnetic recording medium.

Magnetic Tape and Magnetic Disk
 Associative Memory
Time Required to find an item stored in memory can be reduced considerably if
stored data can be identified for access by the content of the data rather than
by address.

A Memory Unit accessed by content is called an Associative Memory or

Content Addressable Memory(CAM).

This type of memory is accessed simultaneously and in parallel on the basis of

data content rather than address. Searches can be done on entire word or on a
specific field within a word.

Associative memory is more expensive than RAM, Each cell must have a
storage capability as well as logic circuits for matching its contents with
external argument.

Application's where the search time is very critical and must be very short.
Hardware Organization
Associative Memory of m Word, n Cells per One Cell Associative Memory
Word
MATCH Logic For One word

MI = X 1+ X 2 + X3 . . .

Xj + K~ j = Xj if Kj = 1
Xj + K~ j = 1 if Kj = 0

MI = (X 1 + K~ 1 ) (X 2 + K~ 2 ) (X 3 + K~ 3 )
 Cache Memory
The Active portions of the program and data are placed in a fast small memory,
The average Memory access time can be reduced, Thus Reducing the execution
time of program.

Cache Access time is less than the Access time of main memory by a factor of 5
to 10.

Cache is the fastest component in the memory hierarchy and approaches the
speed of CPU Components.

Operation of cache: When CPU needs to access the memory. First the cache is
examined If word is found in the cache, it is read from fast memory, if word is
not found main memory is accessed to read the word.
 HIT Ratio

The Performance of Cache is Frequently measured In terms of a quantity called

HIT RATIO.

When CPU refers to the memory and finds the word in cache it is said to
produce one hit, If word is not found in the cache, it is in main memory and it
counts miss.

HIT Ratio:- The ratio of the no. of hits divided by the Total CPU references to
memory (Hit + Miss).

Computer with cache access time is 100ns, while main memory access time of
1000ns.
Memory Mapping
The Transformation of data from main memory to cache memory is referred
to as a mapping process.

There are three types of mapping procedures

1. Associative mapping

2. Direct mapping

3. Set-Associative Mapping
Associative Mapping
Associate memory stores both the address and content of the memory word.

The address value of 15bits is shown in five digit octal number and its
corresponding 12 bit word is shown as a four digit octal number.

CPU Address of 15bit is placed in the argument register and the associative
memory is searched for matched address.

If the address is found corresponding 12bit data is read and sent to the CPU.
address (15 bits)

Argument register

Address Data

01000 3450
CAM 02777 6710
22235 1234
 DIRECT MAPPING
CPU address of 15-Bit is divided in to two fields 9 Least Significant Bits

constitute the index and remaining six bits form Tag field.

Each word in cache consists of data word and its associative tag word.

Index field is used as address for access the cache.

Tag Field of the CPU Address is tag in the word read from cache. If tag matches,

There is a hit or else if it doesnt match its a miss and the required word is read

from main memory . Tag(6) Index(9)

Memory
address Memory data
00000 1220 00 000
32K x 12
000
Index 512 x 12
address Tag Data
00777 2340 Main memory Cache memory
01000 3450 000 00 1220 Address = 15 bits
Address = 9 bits
Data = 12 bits
Data = 12 bits
777
77 777
01777 4560
02000 5670

02777 6710
777 02 6710

Main Memory Cache memory

DIRECT MAPPING
Operation

- CPU generates a memory request with (TAG;INDEX)

- Access Cache using INDEX ; (tag; data)

Direct Mapping with block size of 8 words

Index tag data 6 6 3

000 01 3450 Tag Block Word
Block 0
007 01 6578
010 INDEX
Block 1
017

Block 63 770 02
777 02 6710
 VIRTUAL MEMORY
ADDRESS SPACE : An address used by programmer will be called a Virtual
Memory, Set of such addresses the Address Space.

MEMORY SPACE:- Address in main memory is called Physical Address, Set

of such location is called Memory Space.

Memory Table for Mapping a Virtual Address

 Address Mapping Using Pages
1. Consider a computer with address space 8k and a memory space 4k, Splitting
each into groups of 1K word we obtain 8 pages and four blocks.

2. At any given point of time 4 pages of address space may reside in main memory
in any one of the four blocks.

Address Space and Memory Space Split in to Groups of 1k Word

 Associative Memory Page Table
1. Virtual Address is considered to be represented by two numbers, Page number
address and a line with in a page.

2. Memory page table consists of eight words, one for each page.

3. Address in page table denotes the page number and the content of the word
gives block number where the page is stored in main memory.

4. Pages 1,2,5 and 6 are now available in main memory blocks 3,0,1 and 2.
 ASSOCIATIVE MEORY PAGE TABLE
1. More efficient way is to organize the page table
would be to construct it with number of words
equal to number of blocks in main memory.

2. Size of memory is reduced and each location is

fully utilized.

3. Each entry in associative memory consists of two

fields. The first three bits specify field for storing
page number, The last two bits constitute a field
for storing block number.
 PAGE REPLACEMENT
1. The Program is executed from main memory until it attempts to reference a
page that is still in auxiliary memory, This condition we call it as PAGE FAULT.

2. Page fault occurs the execution of present program is suspended until the
required page is brought in to main memory.

3. When a page fault occurs in a virtual memory system , it signifies that the page
referenced by the CPU is not in main memory. If memory is full, it would be
necessary to remove a page from memory

4. FIFO(First in First OUT) and LRU(Least Recently USED)

5. The page to be removed is easily determined because of identification number

is at the top of FIFO Stack.

6. LRU policy is more difficult to implement, LRU algorithm can be implemented

by associating Counter with every page that is in main memory.
Micro Programmed Control
 Control Memory
1. Two Methods of Implementing Control unit are Hardwired Control and Micro
Programmed Control.

2. Hardwire Control uses fixed instructions, Fixed Logic Blocks, encoders,

Decoders.

3. High Speed, Expensive, Complex, no flexibility of adding new instructions.

4. Micro Programmed Control:- Systematic method for controlling the micro

operation sequences in a digital computer.

5. Control function that specified a micro operation is a binary variable.

6. In Bus organized systems the control signals that specify micro-operations are
group of bits that selects the path in mux, Decoders and in ALUs.
 Control Memory
Control Unit Implementation

Combinational Logic Circuits (Hard-wired)

Micro program
 Control Memory
Control Word:- Control unit initiates a series of sequential steps of Micro
Operations.
Control Variables at any given time can be represented by a string of 1s and 0s
called a control word.
micro programmed Control unit:- Control unit whose binary control variables
are stored in memory.
Micro Instruction:- Each word in control memory contains with in it a micro
instruction.
Micro Instruction Micro Program:- A sequence of micro instructions constitutes
a Micro Program.
Control Memory:- All the control information is stored in Permanently, Control
memory is Read Only Memory.
The use of Micro Program is involves placing all the control variables in words if
ROM.
Control Address Register:- Specifies the address of micro instruction.
 Address Sequencing

Incrementing the control address Register

Unconditional Branch or Conditional branch, Depending on status
bits condition.
A mapping Process from the bits of the instruction to an address fro
control memory.
A facility for subroutine call and return.
Address Sequencing
 CONDITIONAL BRANCH
Load address
Control address register

Increment

MUX
Control memory
...
Status bits
(condition)

Condition select Micro-operations

Next address

If Condition is true, then Branch (address from the next address field of the
current microinstruction)
else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry)
etc.

Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
 MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
0001 AND Routine
ADD 0000
. 0010 LDA Routine
AND 0001
. 0011 STA Routine
LDA 0010 . 0100 BUN Routine
STA 0011
BUN 0100 Control
Storage

Mapping
Bits 10 xxxx 010 Address
10 0000 010 ADD Routine

10 0001 010 AND Routine

10 0010 010 LDA Routine

10 0011 010 STA Routine

10 0100 010 BUN Routine

MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping from the OP-code of an instruction to the address of the
Microinstruction which is the starting microinstruction of its execution micro
program

Machine OP-code
Instruction 1 0 1 1 Address

Mapping bits 0 x x x x 0 0
Microinstruction 0 1 0 1 1 0 0
address
Mapping function implemented by ROM or PLA
OP-code

Mapping memory
(ROM or PLA)

Control address register

Control Memory
 MICROPROGRAM EXAMPLE
Computer Configuration:

MUX
10 0
AR
Address Memory
10 0 2048 x 16
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC
 MACHINE INSTRUCTION FORMAT
Machine Instruction Format
15 14 11 10 0
I Opcode Address

Sample Machine Instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC EA)
STORE 0010 M[EA] AC
EXCHANGE 0011 AC M[EA], M[EA] AC

MicroInstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field
 SYMBOLIC MICROINSTRUCTIONS
Symbols are used in microinstructions as in assembly language
A Symbolic micro program can be translated into its binary equivalent
by a microprogram assembler.

Sample Format :
Five fields: label; micro-ops; CD(Condition For Branching) BR; AD

Label: may be empty or may specify a symbolic address terminated

with colon

Micro-ops: consists of one, two, or three symbols separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

MICROINSTRUCTION FIELD DESCRIPTIONS -
F1,F2,F3
F1 Microoperation Symbol F2 Micro operation Symbol
000 None NOP 000 None NOP
001 AC AC + DR ADD 001 AC AC - DR SUB
010 AC 0 CLRAC 010 AC AC DR OR
011 AC AC + 1 INCAC 011 AC AC DR AND
100 AC DR DRTAC 100 DR M[AR] READ
101 AR DR(0-10) DRTAR 101 DR AC ACTDR
110 AR PC PCTAR 110 DR DR + 1 INCDR
111 M[AR] DR WRITE 111 DR(0-10) PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC AC DR XOR
010 AC AC COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PC PC + 1 INCPC
110 PC AR ARTPC
111 Reserved
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC
 SYMBOLIC MICROPROGRAM
Control Storage: 128 20-bit words
The first 64 words: Routines for the 16 machine instructions
The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
Partial Symbolic Microprogram
Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH

ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH

ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH

ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
 BINARY MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

This microprogram can be implemented using ROM

 DESIGN OF CONTROL UNIT
DECODING ALU CONTROL INFORMATION

Microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 2 1 0 7 6 54 3 2 1 0 7 6 54 3 21 0

AND
ADD AC
Arithmetic
logic and
DRTAC DR
shift unit
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR
MICROPROGRAM SEQUENCER
External
(MAP)

L
I0 3 2 1 0
Input Load
I1 S1 MUX1 SBR
logic
T S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...
 MICROPROGRAM SEQUENCER

1 L L(load SBR with PC)

From I MUX2 Test
CPU SZ T
Input
for subroutine Call
Select BR field I0 logic S0 for next address
of CS I1
S1 selection
CD Field of CM

Input Logic
I0I1T Meaning Source of Address S1S0 L

000 In-Line CAR+1 00 0

001 JMP CS(AD) 10 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 10 1
10x RET SBR 01 0
11x MAP DR(11-14) 11 0

S0 = I 0
S1 = I0I1 + I0T
L = I0I1T
 UNIT 4
Cpmputer Arithmatic
 Arithmetic Algorithms
Arithmetic Algorithm and Procedure for implementing them with digital
Hardware.

Addition, Subtraction, Multiplication and Division for the following types of

data:-

1. Fixed Point Binary data in Signed Magnitude Representation.

2. Fixed Point binary data in Signed 2s Complement.

3. Floating Point Binary Data.

4. Binary Coded Decimal(BCD) data.

 Addition and Subtraction of Signed Magnitude
In addition, when the signs of A and B are identical, add the two magnitudes
and attach the sign of A to the result.

In subtraction, when the signs of A and B are different, add the two
magnitudes and attach the sign of A to the result.

In addition, when signs of A and B are different, compare the magnitudes and
subtract smaller from the larger. Choose the sign of the result to be same as A
if A>B or complement of A if A < B. If the two magnitudes are equal, subtract B
from A and make the sign of result positive.

In subtraction, when signs of A and B are identical, compare the magnitudes

and subtract smaller from the larger. Choose the sign of the result to be same
as A if A>B or complement of A if A < B. If the two magnitudes are equal,
subtract B from A and make the sign of result positive.
Addition and Subtraction of Signed Magnitude
 HARD WARE IMPLEMENTATION

Add Over Flow

Flow Chart for Add and Subtract Operations
Different
Same sign
sign
Same sign Different
sign

A (-B) A+B
A-B A + (-B)
A=5 and B=2
5 2 => 101

110 Different
Same sign
sign
---------
=3 1 011
Here, A = 011 and E=1 A (-B) A+B
A-B A + (-B)

A=2 and B=5

2 5 => 010

011

---------
= -3 101
Here, A = 101 and E=0
=> Correct answer = 2s
complement of A = 011
with As=1
INPUT OUTPUT
ORGANIZATION
 INPUT-OUTPUT ORGANIZATION

Peripheral Devices

Input-Output Interface

Asynchronous Data Transfer

Modes of Transfer

Priority Interrupt

Direct Memory Access

Input-Output Processor

Serial Communication
 PERIPHERAL DEVICES
Input Devices Output Devices
1. Keyboard 1. Card Puncher, Paper Tape Puncher
2. Optical input devices 2. CRT
- Card Reader 3. Printer
- Paper Tape Reader 4. (Impact, Ink Jet, Laser, Dot Matrix)
- Bar code reader 5. Plotter
- Digitizer 6. Analog
- Optical Mark Reader 7. Voice
3. Magnetic Input Devices
- Magnetic Stripe Reader
4. Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
5. Analog Input Devices
 INPUT/OUTPUT INTERFACE
Provides a method for transferring information between internal storage
(such as memory and CPU registers) and external I/O devices
Resolves the differences between the computer and peripheral devices
Peripherals - Electromechanical Devices
CPU or Memory - Electronic Device

Data Transfer Rate

Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed

Unit of Information
Peripherals Byte, Block,
CPU or Memory Word

Data representations may differ

 I/O BUS AND INTERFACE MODULES

Each peripheral has an interface module associated with it

Interface purpose:
1. Decodes the device address (device code)
2. Decodes the commands (operation)
3. Provides signals for the peripheral controller
4. Synchronizes the data flow and supervises
5. the transfer rate between peripheral and CPU or Memory

Typical I/O instruction

 CONNECTION OF I/O BUS
Connection of I/O Bus to CPU

Connection of I/O Bus to One Interface

Data lines
Peripheral
register

Device Buffer register

Output
address peripheral
I/O AD = 1101 Interface
device
and
bus Logic controller

Function code Command

decoder

Sense lines Status

register
Functions of Buses:
I/O BUS AND MEMORY BUS
* MEMORY BUS is for information transfers between CPU and the MM
* I/O BUS is for information transfers between CPU and I/O devices through
their I/O interface
Physical Organizations
Many computers use a common single bus system for both memory and I/O
interface units
Use one common bus but separate control lines for each function
Use one common bus with common control lines for both functions
Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces
I/O Bus
- Communication between CPU and all interface units is via a common I/o bus
- An interface connected to a peripheral device may have a number of data
registers , a control register, and a status register
- A command is passed to the peripheral by sending to the appropriate interface
register
- Function code and sense lines are not needed (Transfer of data, control,
and status information is always via the common I/O Bus)
 ISOLATED vs MEMORY MAPPED I/O
Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations
 I/O INTERFACE

Programmable Interface
- Information in each port can be assigned a meaning
depending on the mode of operation of the I/O device
Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
Allows CPU can define the mode of operation of each port
Programmable Port: By changing the bits in the control register, it is
possible to change the interface characteristics
 ASYNCHRONOUS DATA TRANSFER
Synchronous :
All devices derive the timing information from common clock line

Asynchronous : No common clock

Asynchronous data transfer between two independent units requires that control
signals to be transmitted between the communicating units to indicate the time at which
data is being transmitted
Two Asynchronous Data Transfer Methods:
Strobe pulse :
- A strobe pulse is supplied by one unit to indicate the other unit when the transfer
has to occur

Handshaking:
- A control signal is accompanied with each data being transmitted to indicate the
presence of data
- The receiving unit responds with another control signal to acknowledge receipt of
the data
 STROBE CONTROL
A single control line.
The strobe may be activated by either the source or
the destination unit.

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer : for Data Transfer :

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit unit unit Strobe unit
Strobe

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe
 HANDSHAKING
Strobe Methods :

Source-Initiated : The source unit that initiates the transfer has no way of
knowing whether the destination unit has actually received data

Destination-Initiated :The destination unit that initiates the transfer no way of

knowing whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE method introduces a second

control signal to provide a Reply to the unit that initiates the transfer.

Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units.
If one unit is faulty, data transfer will not be completed. It Can be detected by
means of a timeout mechanism.
SOURCE-INITIATED TRANSFER USING HANDSHAKE
Block Diagram:

Timing Diagram :

Source unit
Sequence of Events : Destination unit

1. Allows arbitrary delays from one state to the next

2. Permits each unit to respond at its own data transfer rate
3. The rate of transfer is determined by the slower unit
 DESTINATION-INITIATED TRANSFER USING
HANDSHAKE
Block Diagram :

Timing Diagram :

Sequence of Events :
 ASYNCHRONOUS SERIAL TRANSFER
Asynchronous serial transfer
Four Different Types of Transfer : Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
Employs special bits which are inserted at both ends of the character code
Each character consists of three parts: 1)Start bit 2)Data bits 3)Stop bits.

A character can be detected by the receiver from the knowledge of 4 rules:

1. When data are not being sent, the line is kept in the 1-state (idle state)
2. The initiation of a character transmission is detected by a Start Bit ,
which is always a 0
3.The character bits always follow the Start Bit
4. After the last character , a Stop Bit is detected when the line returns to
the 1-state for at least 1 bit time
The receiver knows in advance the transfer rate of the bits and the number of
information bits to expect.
 Asynchronous Data Transfer

UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTE

- UART -
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control

Internal Bus
and clock
Chip select
CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD
Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register :
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver Register:
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits :
- Used for I/O flags and for recording errors
Control Register Bits :
- Define baud rate, no. of bits in each character, whether
to generate and check parity, and no. of stop bits
 MODES OF TRANSFER
1. Program-Controlled I/O
2. Interrupt-Initiated I/O
3. Direct Memory Access (DMA)

Program-Controlled I/O :

Read status register

Check flag bit

=0 Polling or Status Checking

flag
=1 Continuous CPU involvement
Read data register
CPU slowed down to I/O speed
Transfer data to memory Simple
Least hardware
no Operation
complete?

yes
Continue with
program
 Modes of Transfer
MODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA
Interrupt Initiated I/O :
- Polling takes valuable CPU time
- Open communication only when some data has to be passed -> Interrupt.
- I/O interface, instead of the CPU, monitors the I/O device
- When the interface determines that the I/O device is ready for data transfer,
it generates an Interrupt Request to the CPU
- Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches
to the service routine to process the data transfer, and then returns to the task it
was performing

DMA (Direct Memory Access) :

-Large blocks of data transferred at a high speed to or from high speed
devices, magnetic drums, disks, tapes, etc.
-DMA controller Interface that provides I/O transfer of data directly to and
from the memory and the I/O device
-CPU initializes the DMA controller by sending a memory address and
the number of words to be transferred
-Actual transfer of data is done directly between the device and memory
through DMA controller
-> Freeing CPU for other tasks
 Priority Interrupt
PRIORITY INTERRUPT
Priority :
- Determines which interrupt is to be served first when two or more requests
are made simultaneously
- Also determines which interrupts are permitted to interrupt the computer
while another is being serviced
- Higher priority interrupts can make requests while servicing a lower priority
interrupt
Priority Interrupt by Software(Polling) :
- Priority is established by the order of polling the devices(interrupt sources)
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow

Priority Interrupt by Hardware :

- Require a priority interrupt manager which accepts all the interrupt requests to
determine the highest priority request
- Fast since identification of the highest priority interrupt request is identified by the
hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine
 Priority Interrupt
HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -
Processor data bus
VAD 1 VAD 2 VAD 3 * Serial hardware priority function
Device 1 Device 2 Device 3 * Interrupt Request Line
PI PO PI PO PI PO To next
device - Single common line
* Interrupt Acknowledge Line
Interrupt request - Daisy-Chain
INT
CPU
Interrupt acknowledge INTACK

One stage of the daisy chain priority arrangement :

Priority in VAD
PI Enable
Vector address
Interrupt Priority out PI RF PO Enable
request RF PO
S Q 0 0 0 0
from device 0 1 0 0
R
1 0 1 0
Delay 1 1 1 1

Interrupt request to CPU

 PARALLEL PRIORITY INTERRUPT
Interrupt register VAD
to CPU
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0
Keyboard 3 I3 0
0
0
0 IEN IST
0
Mask
register 1 Enable

2
Interrupt
to CPU
3
INTACK
from CPU
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables
tristate Bus Buffer to load VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from
different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
 Priority Interrupt

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt when

more than one interrupts take place

Priority Encoder Truth table

Inputs Outputs
I0 I1 I2 I3 x y IST Boolean functions
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1 x = I0' I1'
0 0 0 1 1 1 1 y = I0' I1 + I0 I2
0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3
 Priority Interrupt

INTERRUPT SERVICE ROUTINE

Initial and Final Operations

Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system

Initial Sequence Final Sequence

[1] Clear lower level Mask reg. bits
[2] IST <- 0
[3] Save contents of CPU registers
[4] IEN <- 1
[5] Go to Interrupt Service Routine
[1] IEN <- 0
[2] Restore CPU registers
[3] Clear the bit in the Interrupt Reg
[4] Set lower level Mask reg. bits
[5] Restore return address, IEN <- 1
 DIRECT MEMORY ACCESS
Block of data transfer from high speed devices magnetic disks,
DMA controller - Interface which allows I/O transfer directly between
Memory and Device, freeing CPU for other tasks
CPU initializes DMA Controller by sending memory address and the block
size(number of words)
CPU bus signals for DMA transfer:

ABUS Address bus
Bus request BR DBUS
High-impedence
Data bus
Bus granted BG
CPU
RD Read
(disabled)
WR Write when BG is
Block diagram of DMA controller : enabled
Address bus

Data bus Data bus Address bus

buffers buffers
Internal Bus

DMA select DS Address register

Register select RS
Read RD Word count register
Write WR Control
logic
Bus request BR Control register

Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device
DMA TRANSFER
 Direct Memory Access

DMA I/O OPERATION

Starting an I/O
- CPU executes instruction to
Load Memory Address Register
Load Word Counter
Load Function(Read or Write) to be performed
Issue a GO command

Upon receiving a GO Command DMA performs I/O

operation as follows independently from CPU

Input
[1] Input Device <- R (Read control signal)
[2] Buffer(DMA Controller) <- Input Byte; and
assembles the byte into a word until word is full
[4] M <- memory address, W(Write control signal)
[5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1
[6] If WC = 0, then Interrupt to acknowledge done, else go to [1]

Output
[1] M <- M Address, R
M Address R <- M Address R + 1, WC <- WC - 1
[2] Disassemble the word
[3] Buffer <- One byte; Output Device <- W, for all disassembled bytes
[4] If WC = 0, then Interrupt to acknowledge done, else go to [1]
 INPUT/OUTPUT PROCESSOR - CHANNEL -
- Processor with direct memory access capability
that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Channel can execute a Channel Program
- Stored in the main memory
- Consists of Channel Command Word(CCW)
- Each CCW specifies the parameters needed
by the channel to control the I/O devices and
perform data transfer operations
- CPU initiates the channel by executing an
channel I/O class instruction and once initiated,
channel operates independently of the CPU
 Input/Output Processor

CHANNEL / CPU COMMUNICATION

CPU operations IOP operations

PIPELINING AND VECTOR
PROCESSING
 PIPELINING AND VECTOR PROCESSING
Parallel Processing

Pipelining

Arithmetic Pipeline

Instruction Pipeline

RISC Pipeline

Vector Processing

Array Processors
 PARALLEL PROCESSING
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed

Levels of Parallel Processing

- Job or Program level

- Task or Procedure level

- Inter-Instruction level

- Intra-Instruction level
 PARALLEL COMPUTERS
Architectural Classification
Flynn's classification
Based on the multiplicity of Instruction Streams and Data
Streams
Instruction Stream
Sequence of Instructions read from memory
Data Stream
Operations performed on the data in the processor
Number of Data Streams
Single Multiple

Number of Single SISD SIMD

Instruction
Streams Multiple MISD MIMD
 SISD COMPUTER SYSTEMS
Control Processor Data stream
Memory
Unit Unit

Instruction stream
Characteristics
- Standard von Neumann machine
- Instructions and data are stored in memory
- One operation at a time

Limitations
Von Neumann bottleneck
Maximum speed of the system is limited by the
Memory Bandwidth (bits/sec or bytes/sec)
- Limitation on Memory Bandwidth
- Memory is shared by CPU and I/O
 SIMD COMPUTER SYSTEMS
Memory
Data bus

Control Unit
Instruction stream

P P P Processor units
Data stream
Alignment network

M M M Memory modules

Characteristics

- Only one copy of the program exists

- A single controller executes one instruction at a time
 MISD COMPUTER SYSTEMS

M CU P

M CU P Memory

M CU P Data stream

Instruction stream

Characteristics
- There is no computer at present that can be classified as MISD
 Parallel Processing
TYPES OF SIMD COMPUTERS
Array Processors
- The control unit broadcasts instructions to all PEs, and all active PEs execute the
same instructions
- ILLIAC IV, GF-11, Connection Machine, DAP, MPP

Systolic Arrays
- Regular arrangement of a large number of very simple processors constructed on
VLSI circuits
- CMU Warp, Purdue CHiP
Associative Processors
- Content addressing
- Data transformation operations over many sets of arguments with a single
instruction
- STARAN, PEPE
 MIMD COMPUTER SYSTEMS
P M P M P M

Interconnection Network

Shared Memory

Characteristics
- Multiple processing units

- Execution of multiple instructions on multiple data

Types of MIMD computer systems

- Shared memory multiprocessors

- Message-passing multicomputers
 SHARED MEMORY MULTIPROCESSORS
M M M
Buses,
Interconnection Network(IN) Multistage IN,
Crossbar Switch
P P P
Characteristics
All processors have equally direct access to one large memory address
space.
Example systems
Bus and cache-based systems
- Sequent Balance, Encore Multimax
Multistage IN-based systems
- Ultra computer, Butterfly, RP3, HEP
Crossbar switch-based systems
- C.mmp, Alliant FX/8

Limitations
Memory access latency
Hot spot problem
 MESSAGE-PASSING MULTICOMPUTER
Message-Passing Network Point-to-point connections

P P P

M M M
Characteristics
- Interconnected computers
- Each processor has its own memory, and
communicate via message-passing

Example systems
- Tree structure: Teradata, DADO
- Mesh-connected: Rediflow, Series 2010, J-Machine
- Hypercube: Cosmic Cube, iPSC, NCUBE, FPS T Series, Mark III

Limitations

- Communication overhead
- Hard to programming
 PIPELINING
A technique of decomposing a sequential process into sub operations,
with each sub process being executed in a partial dedicated segment
that operates concurrently with all other segments.

Ai * Bi + Ci for i = 1, 2, 3, ... , 7
Ai Bi Memory Ci

Segment 1
R1 R2

Multiplier
Segment 2

R3 R4

Adder
Segment 3

R5

R1 Ai, R2 Bi Load Ai and Bi

R3 R1 * R2, R4 Ci Multiply and load Ci
R5 R3 + R4 Add
OPERATIONS IN EACH PIPELINE STAGE
 GENERAL PIPELINE
General Structure of a 4-Segment Pipeline

Clock

Input S1 R1 S2 R2 S3 R3 S4 R4

Space-Time Diagram

1 2 3 4 5 6 7 8 9 Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6

2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6
 PIPELINE SPEEDUP
n: Number of tasks to be performed

Conventional Machine (Non-Pipelined)

tn: Time to complete each Task

t1: Time required to complete the n tasks
t 1 = n * tn

Pipelined Machine (k stages)

tp: Clock cycle (time to complete each suboperation )

tk: Time required to complete the n tasks
tk = (k + n - 1) * tp

Speedup
Sk: Speedup

Sk = n*tn / (k + n - 1)*tp
tn
lim Sk = ( = k, if tn = k * tp )
n tp
 PIPELINE AND MULTIPLE FUNCTION UNITS
Example
- 4-stage pipeline
- subopertion in each stage; tp = 20nS
- 100 tasks to be executed
- 1 task in non-pipelined system; 20*4 = 80nS

Pipelined System
(k + n - 1)*tp = (4 + 99) * 20 = 2060nS

Non-Pipelined System
n*k*tp = 100 * 80 = 8000nS

Speedup
Sk = 8000 / 2060 = 3.88

4-Stage Pipeline is basically identicalIto

i the system
I i+1 I i+2 I i+3

with 4 identical function units

Multiple Functional Units P1 P2 P3 P4

 ARITHMETIC PIPELINE
Exponents Mantissas
Floating-point adder a b A B

X = A x 2a R R
Y = B x 2b
Compare Difference
Segment 1: exponents
[1] Compare the exponents by subtraction

[2] Align the mantissa R

[3] Add/sub the mantissa

Segment 2: Choose exponent Align mantissa
[4] Normalize the result
R

Segment 3: Add or subtract

mantissas

R R

Segment 4: Adjust Normalize

exponent result

R R
4-STAGE FLOATING POINT ADDER
A=ax2 B=bx2
p a q b
p q

Stages: Other
Exponent fraction Fraction
S1 subtractor selector
Fraction with min(p,q)
r = max(p,q)
Right shifter
t = |p - q|

S2 Fraction
adder
r c

Leading zero
S3 counter
c
Left shifter
r

d
Exponent
S4 adder

s d
s
C = A + B = c x 2 = d xr 2
(r = max (p,q), 0.5 d < 1)
 INSTRUCTION CYCLE
Six Phases in an Instruction Cycle :
[1] Fetch an instruction from memory
[2] Decode the instruction
[3] Calculate the effective address of the operand
[4] Fetch the operands from memory
[5] Execute the operation
[6] Store the result in the proper place

* Some instructions skip some phases

* Effective address calculation can be done in the part of the decoding phase
* Storage of the operation result into a register is done automatically in the execution
phase

4-Stage Pipeline
[1] FI: Fetch an instruction from memory
[2] DA: Decode the instruction and calculate
the effective address of the operand
[3] FO: Fetch the operand
[4] EX: Execute the operation
 INSTRUCTION PIPELINE
Execution of Three Instructions in a 4-Stage Pipeline

Conventional:

i FI DA FO EX

i+1 FI DA FO EX

i+2 FI DA FO EX

Pipelined :

i FI DA FO EX

i+1 FI DA FO EX

i+2 FI DA FO EX
 INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE

Segment1: Fetch instruction

from memory

Decode instruction
Segment2: and calculate
effective address

yes Branch?
no
Segment3: Fetch operand
from memory

Segment4: Execute instruction

Interrupt yes
Interrupt?
handling
no
Update PC

Empty pipe Step: 1 2 3 4 5 6 7 8 9 10 11 12 13

Instruction 1 FI DA FO EX
2 FI DA FO EX
(Branch) 3 FI DA FO EX
4 FI FI DA FO EX
5 FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX
 Pipeline Conflicts
Resource Conflicts : Access the Memory by two segments at a time

Data Dependency Conflicts : An instruction depends on the result of a previous

instruction, which is not yet available

R1 <- B + C ADD DA B,C + Data dependency

R1 <- R1 + 1
INC DA bubble R1 +1

Branch Difficulties : Branch and other instructions that

changes The value of PC

Hazards in pipelines may make it Pipeline Interlock:

necessary to stall the pipeline Detect Hazards Stall until it is cleared
 STRUCTURAL HAZARDS
Structural Hazards:
Occur when some resource has not been duplicated enough to allow all combinations
of instructions in the pipeline to execute.

Example: With one memory-port, a data and an instruction fetch cannot be initiated
in the same clock.
i FI DA FO EX

i+1 FI DA FO EX

i+2 stall stall FI DA FO EX

The Pipeline is stalled for a structural hazard

- Two Loads with one port memory
- Two-port memory will serve without stall
 DATA HAZARDS
Data Hazards: Occurs when the execution of an instruction depends on the
results of a previous instruction

ADD R1, R2, R3

SUB R4, R1, R5

Data hazard can be deal with either hardware techniques or software

technique
Hardware Technique:
Hardware Interlock:
- hardware detects the data dependencies and delays the scheduling
of the dependent instruction by stalling enough clock cycles
Operand Forwarding (bypassing, short-circuiting):
- A Special hardware used to detect the conflict and avoid it
by routing the data through special path between pipeline segments.

Software Technique:
Delayed load : Compiler used to detect the data conflict and re order the
instructions as necessary to delay the loading of the conflict data by inserting the
no operation instructions.
 CONTROL HAZARDS
Branch Instructions:
- Branch target address is not known until the branch instruction is
completed
Branch Instruction FI DA FO EX
Next Instruction FI DA FO EX

Target address available

Hard ware techniques Dealing with Control Hazards:

* Pre-fetch Target Instruction

* Branch Target Buffer
* Loop Buffer
* Branch Prediction
* Delayed Branch
 Handling of Branch Instructions
Prefetch Target Instruction:
Prefetch the target instructions in addition to the following the branch.
Both are saved until branch decision is made. Then, select the right
instruction stream and discard the wrong one.
Branch Target Buffer(BTB; Associative Memory)
Entry: Address of previously executed branches, target instruction and the next few instructions
After decoding the branch instruction, it searches the associative memory
for address of the instruction
If it is found, fetch the instruction stream in BTB;
If it is not, new stream is fetched and update BTB
Loop Buffer(High Speed Register file)
Storage of entire loop that allows to execute a loop without accessing memory
Branch Prediction
Guessing the branch condition, and fetch an instruction stream based on
the guess. Correct guess eliminates the branch penalty
Delayed Branch
Compiler detects the branch and rearranges the instruction sequence
by inserting useful instructions that keep the pipeline busy in the presence of
a branch instruction
 RISC PIPELINE
RISC :
Machine with a very fast clock cycle that executes at the rate of one
instruction per cycle
Simple Instruction Set
Fixed Length Instruction Format
Register-to-Register Operations
Instruction Cycles of Three-Stage Instruction Pipeline :
Data Manipulation Instructions
I: Instruction Fetch
A: Decode, Read Registers, ALU Operations
E: Write a Register
Load and Store Instructions
I: Instruction Fetch
A: Decode, Evaluate Effective Address
E: Register-to-Memory or Memory-to-Register
Program Control Instructions
I: Instruction Fetch
A: Decode, Evaluate Branch Address
E: Write Register(PC)
 DELAYED LOAD
LOAD: R1 M[address 1]
LOAD: R2 M[address 2]
ADD: R3 R1 + R2
STORE: M[address 3] R3
Three-segment pipeline timing :
Pipeline timing with data conflict :
clock cycle 1 2 3 4 5 6
Load R1 I A E
Load R2 I A E
Add R1+R2 I A E
Store R3 I A E

Pipeline timing with delayed load :

clock cycle 1 2 3 4 5 6 7 The data dependency is taken
Load R1 I A E care by the compiler rather than
the hardware
Load R2 I A E
NOP I A E
Add R1+R2 I A E
Store R3 I A E
 DELAYED BRANCH
Compiler analyzes the instructions before and after the branch and rearranges the
program sequence by inserting useful instructions in the delay steps
Using no-operation instructions :
Clock cycles: 1 2 3 4 5 6 7 8 9 10
1. Load I A E
2. Increment I A E
3. Add I A E
4. Subtract I A E
5. Branch to X I A E
6. NOP I A E
7. NOP I A E
8. Instr. in X I A E

Rearranging the instructions :

Clock cycles: 1 2 3 4 5 6 7 8
1. Load I A E
2. Increment I A E
3. Branch to X I A E
4. Add I A E
5. Subtract I A E
6. Instr. in X I A E
 VECTOR PROCESSING
Vector Processing Applications
Problems that can be efficiently formulated in terms of vectors
Long-range weather forecasting
Petroleum explorations
Seismic data analysis
Medical diagnosis
Aerodynamics and space flight simulations
Artificial intelligence and expert systems
Mapping the human genome
Image processing
Vector Processor (computer)
Ability to process vectors, and related data structures such as matrices
and multi-dimensional arrays, much faster than conventional computers

Vector Processors may also be pipelined

 VECTOR PROGRAMMING
DO 20 I = 1, 100
20 C(I) = B(I) + A(I)

Conventional computer Initialize I = 0

20 Read A(I)
Read B(I)
Store C(I) = A(I) + B(I)
Increment I = i + 1
If I 100 goto 20

Vector computer
C(1:100) = A(1:100) + B(1:100)
 VECTOR INSTRUCTION FORMAT
Vector Instruction Format

Operation Base address Base address Base address Vector

code source 1 source 2 destination length

Pipeline for Inner Product

Source
A

Source Multiplier Adder

B pipeline pipeline
 MULTIPLE MEMORY MODULE AND INTERLEAVING
Multiple Module Memory
Address bus
M0 M1 M2 M3
AR AR AR AR

Memory Memory Memory Memory

array array array array

DR DR DR DR

Data bus

Address Interleaving
e
Different sets of addresses are assigned to different memory modules