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Andreas Gerstlauer
Electrical and Computer Engineering
University of Texas at Austin
gerstl@ece.utexas.edu
Lecture 4: Outline
Un-
timed A B
Un- Approximate- Cycle- Computation
timed timed timed
Source: Lukai Cai, D. Gajski. “Transaction level modeling: An overview”, ISSS 2003
Design methodology
Set of models and transformations between models
EE382V: Embedded Sys Dsgn and Modeling, Lecture 4 © 2008 A. Gerstlauer 5
Top-Down Design Flow
requirements constraints
Product planning
System design
Processor design
Logic design
gates gate delays
Structure Timing
© 2008 A. Gerstlauer 6
Top-Down Design Flow
requirements constraints
Product planning
Computation design
Communication design
Processor design
• Behavioral hierarchy
• Untimed
Communication model
v1
B2 v2 B3
e2
B2 v2 B3
• Message-passing e2
• Abstract communication
and synchronization
• Encapsulate in channel
B2 B3
c2
v1
B2 B3
c2
Specification model
• PE allocation / selection
Computation refinement
Communication refinement
• Variable partitioning
Communication model
Implementation model
B
B11
PE1 • Allocate PEs
PE1 PE2
B
B11
v1
B13snd
cb13 B13rcv
B2 B3
c2
B34rcv cb34
B34snd
B PE1 PE2
B11
v1 v1
v1
3snd B13rcv
cb13
B1
B2 B3
c2
B34rcv cb34
B34snd
v1
cb13 B13rcv
B13snd
v1
B2 B3
c2
B34rcv cb34
B34snd
Annotate behaviors 1
behavior B2( in int v1, ISend c2 )
{
• Simulation feedback void main(void) {
5 B2_DELAY1
waitfor( delay1 ); );
• Synthesis constraints waitfor( B2_DELAY1 );
c2.send( );
waitfor(
10 waitfor( B2_DELAY2
B2_DELAY2 );
);
}
};
B
B11
PE1
• Static scheduling
– Fixed behavior execution order
– Flattened behavior hierarchy
B13snd
• Dynamic scheduling
B2
– Pool of tasks
– Scheduler, abstracted OS
B34rcv
PE1 PE2
B
B11
v1
B2
B3
c2
Specification model
• Network allocation / protocol selection
Computation refinement
Communication refinement
• Protocol stack insertion
Communication model
Implementation model
B2
B3 • Update
c2 communication
PE1 PE2
B
B11
Bus1
v1 cb13 B13rcv
B13snd c2
v1
cb34
B2 B3
B34rcv B34snd
Master Slave
PE1 PE2
B
B11
Bus1
BusProtocol
v1 IBusMaster address[15:0]
B13rcv
IProtocolMaster
IBusSlave
IProtocolSlave
data[31:0]
B13snd ready
v1
B2 B3
B34rcv B34snd
IBusMaster
IProtocolMaster
IBusSlave
IProtocolSlave
data[31:0]
control
PE2Protocol
address[15:0]
IProtocolMaster
PE1Protocol
IBusMaster
IProtocolSlave
IBusSlave
data[31:0]
ready
PE1 PE2
B
B11
address[15:0]
v1 B13rcv
data[31:0]
B13snd v1
control
B2 B3
B34rcv B34snd
Specification model
• Component & bus structure/architecture
Computation refinement
• Top level of hierarchy
• Bus-functional component models Computation model
• Timed
Processor refinement
• Estimated component delays
Implementation model
Specification model
Processor refinement
Implementation model
PE2
B13rcv
v1 PE2_CLK
PE2_CLK
Clock boundaries
B3
PE2_CLK
B34snd
SH r3
v1
L r2, r3,
AD r4 r2
B13snd D
IN
PUS
C r1
B2 H Ff
CAL 3
L r0
POP
B34rcv
S0 PE1Bus PE2Bus
S1
PE2Protocol
IProtocolMaster
PE1Protocol
IBusMaster
IProtocolSlave
addr[15:0] addr[15:0]
IBusSlave
S2 data[31:0] data[31:0] DRV
ready ack ready
S3 ack
S4
S0
Instruction PORTA address[15:0]
Set S1
Simulator PORTB data[31:0]
(ISS) S2
PORTC ready
S3
INTA ack
S4
PE1_CLK PE2_CLK
Implementation model