Digital Logic Design

Combinational Circuits
Objectives
• Introduction
• Analysis arrangement
• Half Adder/Full Adder
• Half Subtractor/Full Subtractor
• BCD to Excess-3 Converter

Ahmad Almulhem, KFUPM 2009

Combinational Gates

MSI Circuit (MSI Component)

• Decoder
• Encoder
• Demultiplexer
• Multiplexer
Programmable Logic Device
• Read-Only-Memory ROM
• Programmable ROM (PROM)
Combinational Gates - Introduction
There are two categories of logic gates
Combinational
Sequential
Combinational logic
Each output depends solely on the current input
Combinational Gates - Introduction
Sequential Logic
Each output depends on both current and the
previous input. Memory (from feed back loop)
contains previous information
Combinational Gates – Analysis
Arrangement
Given combinational logic, can you analyze it’s function?

Step 2
• Mark it’s input and output
• Get the function on each starting gate with the nearest
gate to the input follows to the output
• Draw TT
• Get the function of the circuit – Half Adder
Combinational Gates – Design
Arrangement
Design arrangement
1. What is the problem
Example: Build a full adder which can add two bit.
2. Determine and mark input and output for the circuit
Example: Two input and two output is mark as below:

3. Draw TT
 Combinational Gates – Half
Adder
Design arrangement
4. Get simplest Boolean function. Use K-Map

5. Draw logic diagram

 Combinational Gates – Full
Adder

•Half adder only adds two bits

•To add two binary number, we need to add three
bits (including carry)
•Example:

•Full Adder can be produced from half adder

 Combinational Gates – Full
Adder
Truth table

Use K-map to get SOP form

 Combinational Gates – Full
Adder
•Other method, use algebra manipulation
Combinational Gates – Full
Adder
From the formula,

Full Adder is constructed from two Half Adder

and OR gate
 Full Adder = 2 Half Adders
Manipulating the Equations:
S=(XY)Z
C = XY + XZ + YZ = XY + Z(X  Y )

Think of
Z as a
carry in

Src: Mano’s Book

Combinational Gates – Half
Subtractor
• Half subtractor takes two input bit, let say X, Y to get two-bit
answer which represent X-Y

• Truth Table
Answer either positive or negative
Negative answer is represented by borrow (B) from the next
MSB bit
Output B and D, can also be represented by two’s complement
Combinational Gates – Half
Subtractor
• From TT

• Circuit
Combinational Gates – Full
Subtractor
• Subtraction of two binary numbers need three input
Full subtractor

• Contains borrow input from previous LSB

• Example
 Combinational Gates – Full
Subtractor
• TT

• K-map
Combinational Gates – Full
Subtractor
• Other method, use algebra manipulation
Combinational Gates – Full
Subtractor
With that formula, we get

Full subtractor is constructed from two half

subtractor and OR and NOT gate
Combinational Gates – Code
Converter
Code converter – take input code and
translate it to similar code

Example: BCD converter to Excess-3

Input: BCD digit
Output: Excess-3 digit
Combinational Gates – Code
Converter BCD to Excess-3
Truth table K-Map
Combinational Gates – Code
Converter BCD to Excess-3
BCD-to-Seven-Segment Decoder
- Specification
BCD-to-Seven-Segment Decoder
- Specification
BCD-to-Seven-Segment Decoder
- Specification
a= A’C + A’BD + B’C’D’ + AB’C’

b= A’B’ + A’C’D’ + A’CD + AB’C’

c= A’B + A’D + B’C’D’ + AB’C’

d= A’C^D’ + A’B’C + B’C’D’ + AB’C’ + A’BC’D

e= A’CD’ + B’C’D’

f= A’BC’ + A’C’D’ + A’BD’ + AB’C’

g= A’CD’ + A’B’C + A’BC’ + AB’C’

 Combinational Circuits
Analysis A
B
C
A
F1
?
Given a circuit, find out its function
B
C
A
B

A
C
F2
?
Function may be expressed as:
B
C

Boolean function
Truth table
Design
Given a desired function, determine its circuit
Function may be expressed as: ?
Boolean function
Truth table
 Analysis Procedure
Boolean Expression Approach
A
B
F1
C ABC
A A+B+C
B AB'C'+A'BC'+A'B'C
C
A
B (A’+B’)(A’+C’)(B’+C’)

A
F2
C
F1=AB'C'+A'BC'+A'B'C+ABC
B F2=AB+AC+BC
AB+AC+BC
C
 Analysis Procedure
Truth Table Approach
A =0
0 0
B =0
F1 A B C F1 F2
C =0
0 0 0 0 0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0
 Analysis Procedure
Truth Table Approach
A =0 0
B =0 1 A B C F1 F2
F1
C =1
0 0 0 0 0
A =0 1
B =0 1 0 0 1 1 0
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1
 Analysis Procedure
Truth Table Approach
A =0 0
B =1 1 A B C F1 F2
F1
C =0
0 0 0 0 0
A =0 1
B =1 1 0 0 1 1 0
C =0
1 0 1 0 1 0
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0
 Analysis Procedure
Truth Table Approach
A =0 0
B =1 0 A B C F1 F2
F1
C =1
0 0 0 0 0
A =0 1
B =1 0 0 0 1 1 0
C =1
0 0 1 0 1 0
A =0 0 0 1 1 0 1
B =1

A =0 0 1
F2
C =1

B =1 1
C =1
 Analysis Procedure
Truth Table Approach
A =1 0
B =0 1 A B C F1 F2
F1
C =0
0 0 0 0 0
A =1 1
B =0 1 0 0 1 1 0
C =0
1 0 1 0 1 0
A =1 0 0 1 1 0 1
B =0
1 0 0 1 0
A =1 0 0
F2
C =0

B =0 0
C =0
 Analysis Procedure
Truth Table Approach
A =1 0
B =0 0 A B C F1 F2
F1
C =1
0 0 0 0 0
A =1 1
B =0 0 0 0 1 1 0
C =1
0 0 1 0 1 0
A =1 0 0 1 1 0 1
B =0
1 0 0 1 0
A =1 1 1
C =1
F2 1 0 1 0 1

B =0 0
C =1
 Analysis Procedure
Truth Table Approach
A =1 0
B =1 0 A B C F1 F2
F1
C =0
0 0 0 0 0
A =1 1
B =1 0 0 0 1 1 0
C =0
0 0 1 0 1 0
A =1 1 0 1 1 0 1
B =1
1 0 0 1 0
A =1 0 1
C =0
F2 1 0 1 0 1
1 1 0 0 1
B =1 0
C =0
 Analysis Procedure
Truth Table Approach
A =1 1
B =1 1 A B C F1 F2
F1
C =1
0 0 0 0 0
A =1 1
B =1 0 0 0 1 1 0
C =1
0 0 1 0 1 0
A =1 1 0 1 1 0 1
B =1
1 0 0 1 0
A =1 1 1
C =1
F2 1 0 1 0 1
1 1 0 0 1
B =1 1
C =1 1 1 1 1 1
F1=AB'C'+A'BC'+A'B'C+ABC B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C F =AB+AC+BC
 Digital Logic Design
Combinational Circuits with MSI
Objectives
• Binary Parallel Adder
• BCD Adder
• Magnitude Comparator
• Design of 4-bit magnitude comparator
Bigger Adders
• How to build an adder for n-bit numbers?
• Example: 4-Bit Adder
• Inputs ?
• Outputs ?
• What is the size of the truth table?
• How many functions to optimize?
Bigger Adders
• How to build an adder for n-bit numbers?
• Example: 4-Bit Adder
• Inputs ? 9 inputs
• Outputs ? 5 outputs
• What is the size of the truth table? 512 rows!
• How many functions to optimize? 5 functions
Binary Parallel Adder
To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand
• Use Z in the circuit as a Cin

1 0 0 0
0101
0110
1011
Binary Parallel Adder
To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

Subtraction (2’s Complement)
How to build a subtractor using 2’s
complement?
Subtraction (2’s Complement)
How to build a subtractor using 2’s
complement?

Src: Mano’s Book

S = A + ( -B)
Adder/Subtractor
How to build a circuit that performs both
addition and subtraction?
Adder/Subtractor

0 : Add
1: subtract

Src: Mano’s Book

Using full adders and XOR we can build an Adder/Subtractor!

Binary Parallel Adder (Again)
To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

BCD Adder
BCD digits are valid for decimal numbers 0-9
Addition of two BCD numbers will generate an output,
that may be greater than 1001 (9).
In such cases, the BCD number 0110 is added to the
result as a correction step
When adding two BCD numbers, the maximum result
that can be obtained is:
9 + 9 = 18
If we include a carry in bit, then the maximum result that can
be obtained is: 19 (10011)
Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6
needs to be added to bring them to correct BCD format.
 Adding two BCD numbers –
Truth Table
The truth table defines the
outputs when two BCD
numbers are added
The function F is 1 for all invalid
BCD digits, and therefore acts
as a BCD verifier
To minimize the expression, a 5
variable can be used, or:
-A 4 variable k map can be
used to minimize the function F,
and
-The result is ORed with CO,
since the function is always 1
whenever CO is 1
* From course CD
Adding two BCD numbers –
Minimization

F
Z1Z0
Z3Z2 00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 1 1 1 1
10 0 0 1 1

F = Z3Z2 + Z3Z1 + CO
Adding two BCD numbers –
Circuit
B3 B2B1B0 A3A2A1A0

Cout 4-bit Binary Carry In

Adder
Z3 Z2 Z1 Z0

Correction
Step 4-bit Binary
Adder

S3 S2 S1 S0
Adding two BCD numbers -
Steps
The two 4-bit BCD inputs are added by the 4-bit binary
adder to produce the sum Z3Z2Z1Z0 and a Carry Out
(Cout)
When Cout =0, the correction step executes by adding 0000
to Z3Z2Z1Z0, and the output remains the same
When Cout =1, the correction step adds 0110 to Z3Z2Z1Z0
to generate the corrected output
The output carry is the same as Cout
If additional decimal digits need to be added, the BCD adder
can be cascaded, with the output carry of one phase
connected to the input of the other
Binary Multiplication
Similar to decimal multiplication
Multiplying 2 bits will generate a 1 if both bits are equal to 1, and
will be 0 otherwise. Resembles an AND operation
Multiplying two 2-bit numbers is done as follows:

B1 B0
x A1 A0
----------------
This operation is an
A0B1 A0B0 addition, requires an
A1B1 A1B0 + ADDER
----------------------------------
C3 C2 C1 C0
Binary Multiplication
Therefore, for multiplying two 2-bit numbers, AND
gates and ADDERS will be sufficient

Half Adders
Magnitude Comparator
Definition: A magnitude comparator is a combinational circuit that compares
two numbers A & B to determine whether:
A > B, or
A = B, or
A<B n-bit input n-bit magnitude GT
A comparator
Inputs
First n-bit number A
EQ
Second n-bit number B
n-bit input
Outputs B LE
3 output signals (GT, EQ, LT), where:
GT = 1 IFF A > B
EQ = 1 IFF A = B
LT = 1 IFF A < B
Note: Exactly One of these 3 outputs equals 1, while the other 2 outputs are
0`s
Example 1: Magnitude Comparator (4-bit)

Problem: Design a magnitude comparator that

compares 2 4-bit numbers A and B and determines
whether: 4-bit input 4-bit magnitude GT
comparator
A > B, or A

A = B, or EQ
4-bit input
A<B
B LE
Example 1: Magnitude Comparator (4-bit)

Solution:
Inputs: 8-bits (A = 4-bits , B = 4-bits)
A and B are two 4-bit numbers 4-bit input 4-bit magnitude GT
Let A = A3A2A1A0 , and A comparator

Let B = B3B2B1B0 EQ
4-bit input
Inputs have 28 (256) possible
B
combinations (size of truth table LE

and K-map?)
Not easy to design using conventional
techniques
The circuit possesses certain amount of regularity
⇒ can be designed algorithmically.
Example 1: Magnitude Comparator (4-bit)

Designing EQ:

Define Xi = Ai xnor Bi = Ai Bi + Ai’ Bi’

 Xi = 1 IFF Ai = Bi for i =0, 1, 2 and 3
 Xi = 0 IFF Ai ≠ Bi
Therefore the condition for A = B or EQ=1 IFF
A3= B3 → (X3 = 1), and
A2= B2 → (X2 = 1), and
A1= B1 → (X1 = 1), and
A0= B0 → (X0 = 1).
Thus, EQ=1 IFF X3 X2 X1 X0 = 1. In other words,
EQ = X3 X2 X1 X0
Example 1: Magnitude Comparator (4-bit)

Designing GT and LT:

GT = 1 if A > B:
• If A3 > B3  A3 = 1 and B3 = 0
• If A3 = B3 and A2 > B2
• If A3 = B3 and A2 = B2 and A1 > A1
• If A3 = B3 and A2 = B2 and A1 = B1 and A0 > B0

Therefore,
GT = A3B3‘ + X3 A2 B2‘ + X3 X2 A1 B1‘ + X3 X2 X1A0 B0‘
Similarly, LT = A3’B3 + X3 A2‘B2 + X3 X2 A1’B1 + X3 X2 X1A0’ B0
Example 1: Magnitude Comparator (4-bit)

EQ = X3 X2 X1 X0

GT = A3B3’
+ X3A2B2’
+ X3X2A1B1’
+ X3X2X1A0B0’

LT = B3A3’
+ X3B2A2’
+ X3X2B1A1’
+ X3X2X1B0A0’

4-bit magnitude comparator