Sistem Mikroprosessor

Week 2 Session 1
Microcontroller Architecture

The megaAVR CPU and peripherals (Courtesy of Atmel)

Variety of Processors
 Data size
Nibble 4 bit

Byte 8 bit

Word 16 bit

Long word 32 bit

 8-bit vs 16-bit
• 8 bit microcontroller is kind of
microcontroller having all
characteristics of microcontroller
and its data units are mostly 8 bits
wide.
• 8 bits wide means your CPU can use
8 bit data bus or pipe and can access
the same size data by a single device
instruction.
• For every cycle of instruction its
range is 0 to 255.
• It requires 20mA current to work.
Intel 8008 was the first model having
8 bit micro-controller.
• 8 bit microcontroller shows speed of
12 MIPS at 48 MHz
• 16 bit microcontroller is more
advanced than 8 bit
microcontroller. It is more accurate
and precise in performing
mathematical and technical tasks.
• Unlike 8 bit microcontroller, it uses
16 bits data bus or pipe for a single
instruction.
• For every cycle of instruction its bit
range is extended from 0 to
65,535. As 16 bit controller is two
time more than 8 bit controller, it
can work on two 16 bit numbers.
• It requires 10mA current to
perform.
• 16 bit shows maximum 16 MIPS at
32 MHz
8-bit Microcontroller (Atmega328)
16-bit Microcontroller (Atmega328)
Memory
 Memory
• Read only memory (ROM) – nonvolatile
• Data remains when power is turned off, data are
written into the ROM during its fabrication at the
factory
• PROM- Programmable ROM. Can be programmed
by user but this can only be done once
• EPROM – erasable programmable ROM
• Contents of EPROM can be erased by exposing it
to ultraviolet light
• EEPROM – Electrical Erasable PROM (your USB
memory stick)
 Block diagram of a ROM

ROM interface – address input, data output, /CE – chip enable, /OE – output
enable (for READ operation)
 Memory Read Operation
• To read a ROM, we need to issue the proper
address
• There is a delay between address inputs and data
outputs
• The access time (tACC), chip enable time (tCE), and
chip deselect time (tDF) are important timing
properties
• You need these information for developing a real
computer system
 Timing parameters
• The access time – delay occurs before data
stored at the addressed location are stable at
the outputs (ie how long it takes to access
data). The microprocessor must wait for tACC
before reading the data
 ROM read operation
• Access time is regarded as address to
output delay. Typical value is 250ns
• tCE – represents the Chip Enable to output
delay, usually this is equal to access time
• Deselect time – amount of time the device
takes for data outputs to return to high-Z
state after /OE becomes inactive
 Read operation
tAA= access time tCO= chip select to output delay
tHZ = deselect to output float
Choosing the proper memory
Configuration of ROM for 8-bit bus

How the circuit

operates?
 EEPROM – Electrical Erasable ROM

• Data stored in an EEPROM can be erased

electrically
• Example inside the AduC832 (or 8051)
microcontroller, there are 64KBytes of
EEPROM
 Programming the EPROM
• In an erased EPROM, all cells hold logic 1
• Vpp is in logic 1 for data to be read from EPROM
• Vpp is ON (eg Vpp = 25V for 2716 EPROM) for
programming mode (writing)
• 2716 is a 2Kx8 EPROM
• To write data to the EPROM a 25V signal is
needed so an external device is necessary
 Modern EEPROM

Charges in the
floating gate
represent the data
Control gate blocked
out data = 0

http://www.siliconfareast.com/flash-memory.htm
 FLASH EEPROM

• Flash memory is a later form of EEPROM. In the industry,

there is a convention to reserve the term EEPROM to byte-
wise erasable memories compared to block-wise erasable
flash memories.
• EEPROM occupies more die area than flash memory for the
same capacity, because each cell usually needs a read, a
write, and an erase transistor, while flash memory erase
circuits are shared by large blocks of cells.
• You can read more in:
http://electronics.howstuffworks.com/flash-memory.htm
 Random access memory (RAM)
• Data can be read as well as written into the
memory chip
• Static ram (SRAM) – data remains valid as
long as the power is ON
• Dynamic RAM (DRAM) – needs to
periodically restore (recharge) the data in
each storage location by addressing them
• If storage nodes are not recharged at
regular intervals of time, data would be
lost. This process is called refreshing
A static RAM
The two inverters are cross-
connected to form a latch.
The latch is connected to two bit
lines by transistors T1 and T2.
These transistors act as switches
that can be opened or closed
under control of the word line.
When the word line is at ground
level, the transistors are turned
off and the latch retains its state.
Example, if the logic value at
point X is 1 and at point Y is 0,
this state is maintained as long as
the signal on the word line is at
ground level.
 SRAM circuit
To control
RAM:
CE – chip enable
OE – output enable
(for read operation)
WE – write enable
(for write operation)

From
decoding
logic
 Write-cycle for SRAM
• To write, we must produce the signal in proper
order
• Minimum duration of a write cycle is tWC (write
cycle time )
• Address must remain stable during the whole
cycle
• Chip enable (CE) signal becomes active
• The Write Enable (WE) will be active after the
address setup time tAS elapses
 RAM write operation
• Data should now ready and must be valid
for tDW (data valid to end of write)
• Data should remain valid (tDH) after the
write
• A short recovery period (tWR) takes place
after /WE returns to 1 before the write
cycle is complete (address is removed)
Write cycle
 Timing parameters for a write cycle
Parameter Time (ns)
Tc (rd) read cycle time 120
TWC (wr) write cycle time 120
TWP write pulse width 60
Tsu (A) address set up time 20
Tsu (S) chip select setup time 60
Tsu (D) data setup time 50
Th address hold time 0
Th (D) data hold time 5
 Read Cycle
• Read cycle for RAM is similar to the ROM
• Minimum duration of a read cycle is tRC (read cycle
time)
• Address must remain stable during the whole
cycle
• Chip enable becomes active
• The Enable(s) (CE) will be active after the address
is stable
• Data should now ready
• Data should remain valid after the OE and CE have
been removed
CO – time between
Read Cycle
Valid data and chip enable

OE – time between
Valid data and output enable
 DRAM
• DRAM has a higher density
• Cost less
• Consume less power
• Take up less space
• We can get 64Mx1, 128Mx1 modules
DRAM structure
Needs to periodically restore
(recharge) the data in each storage
location by addressing them
because the data is stored in the
form of a charge on a capacitor as
shown in the circuit.
To store information in this cell,
transistor T is turned on and an
appropriate voltage is applied to
the bit line. This causes a known
amount of charge to be stored in
the capacitor.
 DRAM
• After the transistor is turned off, the charge remains
stored in the capacitor, but not for long.
• The capacitor begins to discharge. During a Read
operation, the transistor in a selected cell is turned on.
• A sense amplifier connected to the bit line detects
whether the charge stored in the capacitor is above or
below the threshold value.
• If the charge is above the threshold, the sense amplifier
drives the bit line to the full voltage representing the logic
value 1. If the sense amplifier detects that the charge is
below the threshold then it pulls the bit line to ground
level to discharge the capacitor fully.
 DRAM
• If storage nodes are not recharged at regular
intervals of time, data would be lost. This
process is called refreshing.
 DRAM

• An example of a DRAM – 2164B

• It is a 64K-bit (64Kx1) device with only 16
pins
• To address 64K address, requires 16-bit
address line
• 16-bit address is divided into two separate
parts: 8-bit row address, and 8-bit column
address. And these are time-multiplexed
 DRAM-2164B

Address bus is time multiplexed

RAS – row address strobe
CAS – column address strobe
 Addressing the DRAM

• The row address is first applied

• /RAS is pulsed to ‘0’ to latch the address into the
device
• The column address is applied and /CAS strobed
to ‘0’
• If RAS is left at ‘0’ after the row address is latched
inside the device, the address is maintained
within the device
DRAM organization

Column

ROW
 DRAM
• Data cells along the selected row can be
accessed by simply supplying successive
column addresses
• This is called page mode accesses
• (How many bits are there in a row?)
• Advantage - faster access of memory is
achieved
Addressing the DRAM-64Kx16 setup
 Refreshing the DRAM
• The DRAM must be refreshed every 2ms
• Refreshing is achieved by cycling through
the row addresses (i.e. generating all the
row address)
• During refreshing, /CAS is at logic ‘1’ and no
data are output
 Example 416800 DRAM

• The 416800 DRAM is 2Mx8 device and the data is

parallel (8-bit) but address is multiplexed divided
into ROW and Column.
• In order to access 2M memory locations, it takes
21 address bits. In the device, the address lines
are multiplexed into: 12 address lines for row
address and column address is only 9-bit.
• The refresh must be done in every 64ms.
416800 DRAM
32Mx8 DRAM

16Kx16K array
Each row has
2K bytes data

To select a row
needs 14 bits

To select a
column 11 bits
System memory configuration
Memory configuration for ADuC832
ADuC832 memory architecture