Microprocessor and

Software System
Microprocessor 8085
 Types of Computers
1. Mainframe –
- Largest and most powerful
- Designed to work at very high speed with large data words.
- Starts with 64 bits and have massive amount of memory.

2. Minicomputer –
- Slow and small in comparison to mainframe
- Used for business data processing, industrial control etc.

3. Microcomputer –
1. Small computers
2. The CPU is usually a single integrated circuit called a microprocessor.
 Structure of Microprocessor

Data Bus

I/P
devices Control bus
Control bus

I/O Ports CPU ROM & RAM

O/P Address Bus

Devices
Memory –
- Consists of RAM and ROM
- Main purpose to store the binary codes for the instructions for execution.

Input/Output –
- Input Allows the computer to take in data from outside and send data to memory.
- Output takes data from memory and send it to output devices.

CPU –
- Also called as microprocessor
- Fetches binary coded instructions from memory, decodes the instructions into a
series of simple actions and carries out these actions into sequence of steps.

Address Bus –
- Consists of 16,20,24 or 32 parallel lines.
- These lines carry address of memory locations.
- The no of memory locations= 2 no of address lines.
e.g. no of address lines=16

Memory locations = 216 =65,536 locations.

Data Bus –
- Consists of 8,16, or 32 parallel signal lines.
- These are bidirectional lines.

Control Bus –
- Consists of 4 to 10 parallel signal lines.
- Typical signals are
- memory read
- memory write
- I/O read and write
Assembly Language –
- Instructions can be written in hexadecimal code. Therefore manufacturer of
Microprocessor has devised a symbolic code for each instructions called
Mnemonics.
Mnemonic – consists of letters which suggest the operation to be performed by
that instruction.

e.g 0011 1100 is 3C in hexadecimal

Can be represented in 8085 as INR A
Where INR – increment
A – Accumulator

Advantages of Assembly Language –

- Writing a program in assembly language is more convenient than in Machine

language.
- The symbols used in this language gives more readability in comparison to
binary language
Disadvantages –

- Assemble language is specific to a particular machine architecture.

- Designed for specific make and model of a microprocessor.
- It is not portable
- Assemble language programs is not as fast as machine language.
Microprocessor Architecture
Microprocessor is a programmable logic device, designed with
registers, flip flops and timing elements. The MP has a set of
instructions designed internally, to manipulate data and communicate
with the peripherals. The process of data manipulation and
communication is determined by logic design of MP, called the
ARCHITECTURE.

All the various functions performed by the MP can be classified in 3

general categories –

1. Microprocessor initiated operations

2. Internal Data operations
3. Peripheral initiated operations
Microprocessor Initiated Operations
Microprocessor performs basically 4 operations –
1. Memory Read : Reads data from memory
2. Memory Write : Write data into memory
3. I/O Read : Accepts data from input devices
4. I/O Write : Sends data to output devices
Microprocessor perform these functions using 3 set of buses-

A15 Address Bus

A0

Micro-
Memory I/P O/P
Processor

D7 Data Bus
D0

Control Bus
Address Bus –
- Consists of 16,20,24 or 32 Unidirectional parallel lines.
- These lines carry address of memory locations.
- The no of memory locations= 2 no of address lines.
e.g. no of address lines=16

Memory locations = 216 =65,536 locations.

Data Bus –
- Consists of 8,16, or 32 parallel signal lines.
- These are bidirectional lines.
- It determines the word length and the register size of a Microprocessor.

Control Bus –
- Consists of 4 to 10 parallel signal lines, Used to provide timing signals.
- Typical signals are
- memory read
- memory write
- I/O read and write
Internal Data Operations
Internal architecture of 8-bit MP determines how and what operations can be
performed with the data-
1. Stores 8-bit data
2. Perform arithmetic and logical operations
3. Test for conditions
4. Sequence the execution of instructions
5. Store data temporarily during execution in the defined read/ write memory
locations called the stack.
For all above operations, MP requires registers, an ALU, Buses.

Accumulator (8) Flag Registers

B (8) C (8)

D (8) E (8)
H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Address Lines 16
Data Lines 8
Registers
- 8085 has 6- general purpose registers to store 8-bit data during program
execution.
- Registers are B,C,D,E,H,L
- These registers can be combined as pair BC, DE, HL to perform 16-bit
operations.
- Registers are programmable i.e. it can used to load or transfer data from
registers by using instructions.
Accumulator
- 8-bit register main part of ALU.
- Identified by A
Flags
- used for the testing for data conditions.
- 8086 has 5 flags to indicate 5 different types of data conditions.
Z (zero), Carry (CY), Sign (S), Parity (P), Auxiliary Carry (AC)
1. Sign Flag (S)– after execution of an arithmetic or logical operation, if bit D7 of
the result is 1, the sign flag will be set (-ive result) else reset (+ive result).

2. Zero Flag (Z) – this flag is et if ALU operations result is 0, else reset.

3. Auxiliary Carry Flag (AC) – if the carry is generated in BCD binary operation
from D3 bit to D4 bit then flag will be set.

4. Parity Flag (P) – if the result has an even no. of 1s in the result the it is called as
even parity and parity flag will be set, else reset.

5. Carry Flag (CY) – if result has carry then flag will be set else reset.
Program Counter (PC)
- 16- bit register used for sequencing execution of instructions.
- This register is a memory pointer.
- Used to point to the memory address from which the next byte is to be
fetched.
- When byte is being fetched the PC incremented by 1 to point next
location.

Stack Pointer (SP)

- 16- bit register used as a memory pointer.
- Points to a memory location in R/W memory called the stack.
- SP has the address of TOP of the stack.
Peripheral or Externally Initiated Operations
External devices (or signals) can initiate the following operations, for which
individual pins on the MP chip are assigned.
Reset, Interrupt, Ready, Hold.

1. Reset – when it is activated , all internal operations are suspended and

program counter is cleared.
2. Interrupt – The MP can be interrupted from the normal execution of
instructions and asked to execute other instructions called – service routine.
3. Ready – if the signal at this state is Low, the MP enters into a wait state. This
signal is used to synchronize the speed of MP with low speed external
devices.
4. Hold – When any external device needs data bus or address bus to use it
activates this signal to inform MP. After this if MP is not using buses it
relinquishes buses and transfer control to external device.
8085 Microprocessor Pin Diagram
- 8-bit general purpose MP capable of addressing 64K memory.
- Has 40 pins.
- Requires +5v single power supply.
- Operate with 3MHZ single phase clock.

According to pin layout all signals produced or received by the MP can be

classified into 6 groups-

1. Address Bus
2. Multiplexed Address /Data bus
3. Control and status signals
4. Power Supply and Frequency Signals
5. Interrupt and peripheral initiated signals.
6. Serial I/O ports.
 3 MHG +5v GND
Serial I/O Ports
5 1 2 40 20 28
SID
High order
4 address bus
SOD
21

6 19
TRAP Multiplexed
Addr/Data Bus
Interrupt and Externally

RST 7.5 7 12

RST 6.5 8 30 ALE

9
RST 5.5
Initiated Signals

29 S0
INTR 10

Control Signals
33 S1

35 34 IO/M
Ready

HOLD 39 32 RD

36 31 WR
RESET IN
11 INTA

3 37 38 HLDA

Reset Out CLK out

Address Bus (A8-A15) pin 21-28– unidirectional and used high order
address bus
Multiplexed Address/ Data bus-(AD0-AD7) pin 12-19- Bidirectional,
server dual purpose, used as low order address bus and data bus.
Control and Status Signals –
ALE(pin 30)- Address Latch Enable, it indicates that bits on AD7-AD0 are
address bits, if it is high i.e address bus else data bus.
RD’ (pin)- (Read 32) this signal indicates that selected I/O device is to be
read and data are available on data bus.
WR’ (write) (pin 31) – this signal indicates that the data on data bus are to
be written into a memory or selected device.
IO/M’ (pin 34) – used to differentiate between I/O and Memory operations.
S1 and S0 (pin 33, 29) – s1 is called as read signal while s0 is write signal,
these signal shows which kind of operation is performing by MP.
Power supply and frequency signals –
VCC (pin 40)- +5V power supply is required.
Vss (pin 20)- ground reference.
X1, X2 (pin 1,2) – A crystal is connected at these 2 pins to generate 3 MHZ
frequency.
CLK Out (pin 37) – used as system clock for other devices .
Interrupt and Peripheral Initiated Signals –
- 8085 has 5 interrupts
INTR (pin10)– interrupt request
INTA’ (pin 11) – Interrupt acknowledgement
RST 7.5, 6.5 and 5.5 (pin 7-9) – restart interrupts used to transfer the program
control to specific memory location.
TRAP (pin - 6) – it is a general interrupt request.
HOLD (pin 39)– indicates request for address or data bus.
HLDA (pin 38) – acknowledge for hold signal.
Ready (pin 35) – delay the MP to synchronize the speed with external low speed
device.
RESET IN’ (pin 36) – when it is low PC is set to 0 and MP is disabled
RESET OUT’ (pin 3)- MP is become enabled.
Serial I/O ports –
SID (pin 5) – serial input port.
SOD (pin 4) – Serial Output Port
 8085 Memory
- It stores binary instructions and data for the MP.
- Memory is made of registers, and each register can store no. of bits
called memory word.

Memory Organization

For 8-bit MP the memory word length is 8-bit to communicate with

memory MP does following operations-
- Select the chip
- Identify the register
- Read from or write into the register.
R/W
CS
Control Logic

111

Address Lines 110

Internal Decoder

A2 101

Memory Address
A1
100
A0
011

010

001

000

D7 to D0 I/O Lines
CS- chip select
R/W – read write
Memory chip of 8 registers with 3 address lines
To read from or write into a memory location the MP places the address on
the address bus.
- The decoder decodes the address and identifies the register
- The control signal R/W enables the I/O lines, and the data byte is either
read from or write into the memory location.
- cs signal used to select the chip

8085 has 2 types of memory chip –

1. Read/write memory (RAM)

2. Read only memory (EPROM)

- Both are 256 bytes

- 2 control signals are used MEMR’ and MEMW’.
Input / Output 8085
- The MP communicate with outside world through such devices
- The MP accepts binary data as I/P from devices like – keyboard,
Floppy etc.
- Display to output devices – LDE, Printers

There are 2 methods through which MP communicate with I/O devices

1. Peripheral I/O
2. Memory Mapped I/O

Peripheral I/O
- 2 instructions In and OUT are used for data transfer
- MP uses 8 address lines to send address of I/O devices
- IOR’ and IOW’ control signals are used.

Memory Mapped I/O

- MP uses 16 address lines
- MEMR’ and MEMW control signals are used.
 Chapter 12
8085 Interrupts
 Interrupts
• Interrupt is a process where an external device can get
the attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.

• Classification of Interrupts
– Interrupts can be classified into two types:
• Maskable Interrupts (Can be delayed or Rejected)
• Non-Maskable Interrupts (Can not be delayed or Rejected)

• Interrupts can also be classified into:

• Vectored (the address of the service routine is hard-wired)
• Non-vectored (the address of the service routine needs to be supplied
externally by the device)
 Interrupts
• An interrupt is considered to be an emergency signal
that may be serviced.
– The Microprocessor may respond to it as soon as possible.

• What happens when MP is interrupted ?

– When the Microprocessor receives an interrupt signal, it
suspends the currently executing program and jumps to an
Interrupt Service Routine (ISR) to respond to the incoming
interrupt.
– Each interrupt will most probably have its own ISR.
 Responding to Interrupts
• Responding to an interrupt may be immediate or delayed
depending on whether the interrupt is maskable or non-
maskable and whether interrupts are being masked or
not.

• There are two ways of redirecting the execution to the

ISR depending on whether the interrupt is vectored or
non-vectored.
– Vectored: The address of the subroutine is already known to the
Microprocessor
– Non Vectored: The device will have to supply the address of the
subroutine to the Microprocessor
 The 8085 Interrupts
• When a device interrupts, it actually wants the MP to
give a service which is equivalent to asking the MP to
call a subroutine. This subroutine is called ISR (Interrupt
Service Routine)
• The ‘EI’ instruction is a one byte instruction and is used
to Enable the interrupts.
• The ‘DI’ instruction is a one byte instruction and is used
to Disable the interrupts.
• The 8085 has a single Non-Maskable interrupt.
– The non-maskable interrupt is not affected by the value of the
Interrupt Enable flip flop.
 The 8085 Interrupts
• The 8085 has 5 interrupt inputs.
– The INTR input.
• The INTR input is the only non-vectored interrupt.
• INTR is maskable using the EI/DI instruction pair.

– RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.

– TRAP is the only non-maskable interrupt in the 8085

• TRAP is also automatically vectored
 The 8085 Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
 8085 Interrupts
TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA
 Interrupt Vectors and the Vector
Table
• An interrupt vector is a pointer to where the ISR
is stored in memory.
• All interrupts (vectored or otherwise) are
mapped onto a memory area called the Interrupt
Vector Table (IVT).
– The IVT is usually located in memory page 00
(0000H - 00FFH).
– The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when an
interrupt arrives.
• Example: Let , a device interrupts the
Microprocessor using the RST 7.5 interrupt line.
– Because the RST 7.5 interrupt is vectored,
Microprocessor knows , in which memory location it
has to go using a call instruction to get the ISR
address. RST7.5 is knows as Call 003Ch to
Microprocessor. Microprocessor goes to 003C
location and will get a JMP instruction to the actual
ISR address. The Microprocessor will then, jump to
the ISR location
– The process is illustrated in the next slide..
 The 8085 Non-Vectored Interrupt
Process
1. The interrupt process should be enabled using the EI
instruction.
2. The 8085 checks for an interrupt during the execution of every
instruction.
3. If INTR is high, MP completes current instruction, disables the
interrupt and sends INTA (Interrupt acknowledge) signal to the
device that interrupted
4. INTA allows the I/O device to send a RST instruction through
data bus.
5. Upon receiving the INTA signal, MP saves the memory location
of the next instruction on the stack and the program is
transferred to ‘call’ location (ISR Call) specified by the RST
instruction
 The 8085 Non-Vectored Interrupt
Process
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further
interrupt within the program.
8. RET instruction at the end of the ISR allows the MP to
retrieve the return address from the stack and the
program is transferred back to where the program was
interrupted.

** See the example of the Class that showed how interrupt

process works for this 8 steps **
 The 8085 Non-Vectored Interrupt
Process
• The 8085 recognizes 8 RESTART instructions: RST0 -
RST7.
– each of these would send the execution to a predetermined
hard-wired memory location:
Restart Equivalent to
Instruction
RST0 CALL 0000H
RST1 CALL 0008H
RST2 CALL 0010H
RST3 CALL 0018H
RST4 CALL 0020H
RST5 CALL 0028H
RST6 CALL 0030H
RST7 CALL 0038H
 Restart Sequence
• The restart sequence is made up of three
machine cycles
– In the 1st machine cycle:
• The microprocessor sends the INTA signal.
• While INTA is active the microprocessor reads the data lines
expecting to receive, from the interrupting device, the opcode
for the specific RST instruction.
– In the 2nd and 3rd machine cycles:
• the 16-bit address of the next instruction is saved on the
stack.
• Then the microprocessor jumps to the address associated
with the specified RST instruction.
 Timing Diagram of Restart
Sequence
• See the Page 380, Figure 12.2, of your
Text Book for the Timing Diagram of the
RST instruction
 Hardware Generation of RST
Opcode
• How does the external device produce the
opcode for the appropriate RST
instruction?
– The opcode is simply a collection of bits.
– So, the device needs to set the bits of the
data bus to the appropriate value in response
to an INTA signal.
 Hardware Generation of RST
The following is an
Opcode
example of generating
RST 5:

RST 5’s opcode is EF =

D D
76543210
11101111
 Hardware Generation of RST Opcode
• During the interrupt acknowledge machine cycle, (the 1st
machine cycle of the RST operation):
– The Microprocessor activates the INTA signal.
– This signal will enable the Tri-state buffers, which will place the
value EFH on the data bus.
– Therefore, sending the Microprocessor the RST 5 instruction.

• The RST 5 instruction is exactly equivalent to CALL

0028H
 Issues in Implementing INTR
Interrupts
• How long must INTR remain high?
– The microprocessor checks the INTR line one clock cycle before
the last T-state of each instruction.
– The INTR must remain active long enough to allow for the
longest instruction.
– The longest instruction for the 8085 is the conditional CALL
instruction which requires 18 T-states.
• Therefore, the INTR must remain active for 17.5 T-
states.
• If f= 3MHZ then T=1/f and so, INTR must remain active
for [ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].
 Issues in Implementing INTR
Interrupts
• How long can the INTR remain high?
– The INTR line must be deactivated before the EI is
executed. Otherwise, the microprocessor will be
interrupted again.
– Once the microprocessor starts to respond to an
INTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as

the INTA signal is received.
Issues in Implementing INTR Interrupts
• Can the microprocessor be interrupted again before the
completion of the ISR?
– As soon as the 1st interrupt arrives, all maskable interrupts are
disabled.
– They will only be enabled after the execution of the EI
instruction.

Therefore, the answer is: “only if we allow it to”.

If the EI instruction is placed early in the ISR, other
interrupt may occur before the ISR is done.
 Multiple Interrupts & Priorities
• How do we allow multiple devices to interrupt
using the INTR line?
– The microprocessor can only respond to one signal
on INTR at a time.
– Therefore, we must allow the signal from only one of
the devices to reach the microprocessor.
– We must assign some priority to the different devices
and allow their signals to reach the microprocessor
according to the priority.
 Multiple Interrupts & Priorities
• Note that the opcodes for the different RST instructions
follow a set pattern.
• Bit D5, D4 and D3 of the opcodes change in a binary sequence
from RST 7 down to RST 0.
• The other bits are always 1.
• This allows the code generated by the 74366 to be used directly to
choose the appropriate RST instruction.

• The one draw back to this scheme is that the only way to
change the priority of the devices connected to the
74366 is to reconnect the hardware.
Multiple Interrupts and Priority

See the Text Book, Page 384-385

for the detailed explanation of the
Multiple interrupt process
The 8085 Maskable/Vectored Interrupts
• The 8085 has 4 Masked/Vectored interrupt inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the following table:
Interrupt Vector

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors for the RST
instructions. That’s why they have names like RST 5.5 (RST 5 and a
half).
Masking RST 5.5, RST 6.5 and
RST 7.5
• These three interrupts are masked at two
levels:
– Through the Interrupt Enable flip flop and the
EI/DI instructions.
• The Interrupt Enable flip flop controls the whole
maskable interrupt process.
– Through individual mask flip flops that control
the availability of the individual interrupts.
• These flip flops control the interrupts individually.
 The 8085 Maskable/Vectored Interrupt
Process
1. The interrupt process should be enabled using the EI
instruction.
2. The 8085 checks for an interrupt during the execution of
every instruction.
3. If there is an interrupt, and if the interrupt is enabled using
the interrupt mask, the microprocessor will complete the
executing instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call instruction that
sends the execution to the appropriate location in the
interrupt vector table.
 The 8085 Maskable/Vectored Interrupt
Process
5. When the microprocessor executes the call instruction, it
saves the address of the next instruction on the stack.
6. The microprocessor jumps to the specific service routine.
7. The service routine must include the instruction EI to re-
enable the interrupt process.
8. At the end of the service routine, the RET instruction
returns the execution to where the program was
interrupted.
 Manipulating the Masks
• The Interrupt Enable flip flop is manipulated
using the EI/DI instructions.

• The individual masks for RST 5.5, RST 6.5 and

RST 7.5 are manipulated using the SIM
instruction.
– This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.
 How SIM Interprets the Accumulator
7 6 5 4 3 2 1 0

M5.5
M6.5
M7.5
MSE
SDO

R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask

Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to SOD pin 1 - Set the masks according
to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

 SIM and the Interrupt Mask
• Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2
is the mask for RST 7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.

• Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask.
• If it is set to 0 the mask is ignored and the old settings remain.
• If it is set to 1, the new setting are applied.
• The SIM instruction is used for multiple purposes and not only for setting
interrupt masks.
– It is also used to control functionality such as Serial Data Transmission.
– Therefore, bit 3 is necessary to tell the microprocessor whether or not the
interrupt masks should be modified
 SIM and the Interrupt Mask
• The RST 7.5 interrupt is the only 8085 interrupt that has memory.
– If a signal on RST7.5 arrives while it is masked, a flip flop will remember
the signal.
– When RST7.5 is unmasked, the microprocessor will be interrupted even
if the device has removed the interrupt signal.
– This flip flop will be automatically reset when the microprocessor
responds to an RST 7.5 interrupt.

• Bit 4 of the accumulator in the SIM instruction allows explicitly

resetting the RST 7.5 memory even if the microprocessor did not
respond to it.
• Bit 5 is not used by the SIM instruction
Using the SIM Instruction to Modify the
Interrupt Masks
• Example: Set the interrupt masks so that RST5.5 is
enabled, RST6.5 is masked, and RST7.5 is enabled.
– First, determine the contents of the accumulator
- Enable 5.5 bit 0 = 0

M7.5
M6.5
M5.5
SDO

MSE
R7.5
SDE
XXX
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
- Allow setting the masks bit 3 = 1 0 0 0 0 1 0 1 0
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0
- Don’t use serial data bit 6 = 0 Contents of accumulator are: 0AH
- Serial data is ignored bit 7 = 0

EI ; Enable interrupts including INTR

MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks
 Triggering Levels

• RST 7.5 is positive edge sensitive.

• When a positive edge appears on the RST7.5 line, a logic 1 is
stored in the flip-flop as a “pending” interrupt.
• Since the value has been stored in the flip flop, the line does not
have to be high when the microprocessor checks for the interrupt to
be recognized.
• The line must go to zero and back to one before a new interrupt is
recognized.

• RST 6.5 and RST 5.5 are level sensitive.

• The interrupting signal must remain present until the microprocessor
checks for interrupts.
How RIM sets the Accumulator’s
different bits
7 6 5 4 3 2 1 0

M6.5
M5.5
M7.5
P6.5
P7.5

P5.5
SDI

IE
}
RST5.5 Mask
Serial Data In 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
RST5.5 Interrupt Pending
RST6.5 Interrupt Pending
RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop
 The RIM Instruction and the Masks
• Bits 0-2 show the current setting of the mask for each of
RST 7.5, RST 6.5 and RST 5.5
• They return the contents of the three mask flip flops.
• They can be used by a program to read the mask settings in order
to modify only the right mask.

• Bit 3 shows whether the maskable interrupt process is

enabled or not.
• It returns the contents of the Interrupt Enable Flip Flop.
• It can be used by a program to determine whether or not interrupts
are enabled.
The RIM Instruction and the Masks
• Bits 4-6 show whether or not there are pending
interrupts on RST 7.5, RST 6.5, and RST 5.5
• Bits 4 and 5 return the current value of the RST5.5 and
RST6.5 pins.
• Bit 6 returns the current value of the RST7.5 memory flip
flop.

• Bit 7 is used for Serial Data Input.

• The RIM instruction reads the value of the SID pin on the
microprocessor and returns it in this bit.
 Pending Interrupts
• Since the 8085 has five interrupt lines,
interrupts may occur during an ISR and
remain pending.
– Using the RIM instruction, it is possible to can
read the status of the interrupt lines and find if
there are any pending interrupts.

– See the example of the class

 TRAP
• TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot be disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again until it goes
low, then high again.

• TRAP is usually used for power failure and emergency

shutoff.
 The 8085 Interrupts

Interrupt Masking Triggering

Maskable Vectored
Name Method Method

Level
INTR Yes DI / EI No
Sensitive

RST 5.5 / DI / EI Level

Yes Yes
RST 6.5 SIM Sensitive

DI / EI Edge
RST 7.5 Yes Yes
SIM Sensitive
Level &
TRAP No None Yes Edge
Sensitive
 Instruction Set
Classification of Instruction Set by Operation

An instruction is a binary pattern designed inside a MP to perform a specific

function.
• Data transfer operations
• Arithmetic Operations
• Logical Operations
• Branching
• Machine control
Data Transfer – this group of instructions copies data from one location to another
location.
e.g. copy contents, load contents etc.

Arithmetic Instructions – Addition, Subtraction, increment and decrement.

Logical Instructions – AND, OR, Ex-OR, Rotate left shift and right shift, compare
and complement

Branching – Jump, Call , Return etc

Machine Control – Halt, interrupt etc.

Instruction Format

Each instruction has 2 parts –

1. Task to performed (Opcode)
2. Data to be operated (Operand)- 8bit or 16-bit

Instruction Size
There can be three size instructions –
1. One byte
2. Two byte
3. Three byte
One byte – when opcode and operand is stored in the same byte
e.g. reg to reg operations, reg pair and Memory is used
Two Byte – when first byte is opcode and 2nd byte is operand of 8bit

Three byte - when first byte is opcode and 2nd byte and 3rd byte is operand
of 16bit

Control and Status Signals –

8085 operations IO/M’ S1 S0 RD’ WR’

1. Opcode fetch 0 1 1 0 1
2. Memory Read 0 1 0 0 1
3. Memory Write 0 0 1 1 0
4. I/O Read 1 1 0 0 1
5. I/O Write 1 0 1 1 0
Important definitions

1. Instruction Cycle – time required to complete execution of an instruction.

2. Machine Cycle – Time required to complete the operation of access

memory or I/O

3. T-States – defined as one subdivision of the operation performed in 1

clock period.
 8085 instruction sets –

Data Transfer –

1. MOV Rd, Rs - 1 byte instruction, copy data from Rs -> Rd

MOV B,A

2. MVI Rd, 8bit - 2 byte instruction, stores 8bit data into

reg.

MVI H, 32H

3. OUT 8bit - 2 byte instruction, Display contents of

accumulator into output port.
Out 01H
4. In 8bit - 2byte instruction, take input and store into Accumulator.

In 01H

Arithmetic Instructions –

1. Add Reg - 1 byte instruction, add contents of reg with

Accumulator A<- A + Reg

ADD B
2. ADI 8bit - 2 byte instruction. Add 8 bit data into A

ADI 32H
3. SUB Reg - 1 byte instruction, Subtract contents of reg with
Accumulator A<- A - Reg

SUB B
4. SUI 8bit - 2 byte instruction. subtract 8 bit data into A

SUI 32h
5. INR R - 1 byte, increment reg by one R<- R+1

INR B
6. DCR R - 1 byte, decrement reg by one R<- R-1

DCR B

Example – Write a program to perform following Operations –

- Load 8BH into D
- Load 0FH into C
- Increment C by one
- Add C and D
- Display result at port1
Memory Location Mnemonics

2000 MVI D, 8BH

2001
2002 MVI C, 0FH
2003
2004 INR C
2005 MOV A,C
2006 ADD D
2007 OUT port1
2008
2009 HLT

Total Size – 10 Bytes