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System Cache
Is cached by
àain àemory
Is cached by
Virtual àemory
(residing on disk)
MM.
The virtual address is divided into a page offset and a
virtual page number:
frame0
page0 frame1
page1 frame2
page2 frame3
page3 Physical àemory
page4
page5
Virtual àemory Table Và (on Disk Space)
Page Table Contents
The page table also contains a Valid Bit (V)
M
(V=1) or still on
disk (V=0).
page0 1 2
page1 0 (2,1,7)
page2 1 0
page3 1 1
page4 0 (7,2,9)
page5 1 3
page0 1 2
page1 0 (2,1,7)
page = 2
page2 1 0 frame=0
page3 1 1
page4 0 (7,2,9)
page5 1 3
Physical Address
Accessing Data
4. Access main memory using the physical address.
± A page consists of many bytes (e.g. 32KB)
± The page offset tells us exactly which byte of these 32KB we are
accessing.
Similar to the idea of block offset and byte offset in caches
Page Fault
½
1. In this case, V=0, and the page table contains the disk
address of the page (e.g. page1 in the previous example is
still at side 2, track 1, block 7 (2,1,7) of the disk.
2. Find a free physical page
- if none are available, apply a replacement policy (e.g. LRU) to
find one.
3. Load the virtual page into the physical page.
- Set the V flag, and update the page table to show which
physical page the virtual page has gone to.
Behavior of Page Replacement Algorithms
Example: 3
M
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M
M
3
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Fully Associative
± New page table entries go into the next free TLB block,
or a block is replaced if there are none.
Note that only page table entries with V=1 are
written to the TLB!
The page table entries already in the TLB are not
usually updated, so no need to consider write-
through or write-back
± Exceptional cases: page aliasing, where more than 1
page can refer to the same Physical Page.
Translation Look-aside Buffer
The tags used in the TLB is the virtual page number of a
virtual address.
All TLB blocks are searched for the page. If found, we have
a TLB hit and the physical page number is read from the
TLB. This is joined with the page offset to form the
physical address.
If not found, we have a TLB miss. Then we must go to the
page table in main memory to get the page table entry there.
Write this entry to TLB.
Translation Look-aside Buffer
Complication
± If we have a TLB miss and go to main memory to get the page
table entry, it is possible that this entry has a V of 0 - page fault.
± In this case we must remedy the page fault first, update the page
table entry in main memory, and then copy the page table entry
into TLB. The tag portion of TLB is updated to the page of the
virtual address.
Note that the TLB must also have a valid bit V to indicate if
the TLB entry is valid (see cache section for more details on
the V bit.)
Integration Cache, àain àemory and
Virtual àemory
Suppose a Virtual Address | is generated by the CPU
(either from PC for instructions, or from ALU for and
instructions).
1. Perform address translation from Virtual Address to Physical
Address
(a) Look up TLB or page table (see previous slides). Remedy page
fault if necessary (again, see previous slides).
2. Use the physical address to access the cache (see cache notes).
3. If cache hit, read the data (or instruction) from the cache.
4. If cache miss, read the data from main memory.
Use of a Translation Lookaside Buffer
Integration Cache, àain àemory and
Virtual àemory
Note that a page-fault in Và will necessarily cause a cache
miss later on (since the data wasn¶t in physical memory, it
cannot possibly be in cache!)
Can optimize algorithm in event of page fault:
1. Remedy the page fault.
2. Copy the data being accessed directly to cache.
3. Restart previous algorithm at step 3.
This optimization eliminates 1 unnecessary cache access
that would definitely miss.
Page Table Size
A Virtual àemory System was implemented for a àIPS
workstation with 128àB of main memory. The Virtual
àemory size is 1GB, and each page is 32KB. Calculate the
size of the page table.
Page Table Size
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àaking Address Translation Fast
A cache for address translations: translation lookaside
buffer
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TLBs and caches
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