Modeling The Impact of PCB Traces On The Performance of An RF Amplifier in An ASIC With The Help of CST-Studio Full Field EM Simulations and Cadence Virtuoso Co-Simulations

Modeling the Impact of PCB traces on
the Performance of an RF Amplifier in an

ASIC with the help of CST-Studio Full
Field EM Simulations and Cadence
Virtuoso Co-Simulations
Harman Malhotra
Supervisor: Sreekesh Lakshminarayanan

TU Darmstadt
Integrated Electronic Systems Lab
Prof. Dr.-Ing. Klaus Hofmann
Merckstr. 25, 64283 Darmstadt, Germany
Integrated Electronic
27.04.2017 | TU Darmstadt | Integrated Electronic Systems Lab | Harman Malhotra | 1 Systems Lab
Outline
• Introduction & Motivation
• ASIC Chip
• RF Amplifier-Design & Modelling Losses
• Full Field EM Simulation using CST
• CST EM Simulation Results
• CST to Cadence Import
• Co-Simulation in Cadence
• Co-simulation Results
• Conclusion and Future Work
Introduction & Motivation-I
Optical Fibre Fibre to the x (FTTx)
• Larger Bandwidth • FTTP {FTTH, FTTB}
• Low Loss → Longer Distances • FTTN
• Lower Maintenance Costs • FTTC
Wireless/
Passive Optical Network (PON) FTTH λ2 Celltower
λ1
λ3 FTTB
Central λ1λ2 λ3 λ4 … λN Passive

Remote λ4
Office
FTTC
Node Ethernet
Lakshminarayanan [1]
λN FTTN
Introduction & Motivation-II
Optical Transceiver Module SFP (Small form-factor pluggable)
• Receiver • Interface between network device
and fibre optic
• 8.5mm x 13.4mm x 56.5mm
Finisar [2]
• Transmitter
m
8.5 mm
m
.5
56
13
.4
mm
Mixed-Signal ASIC
• RF signal chain
• Wavelength control for Laser Diode
• Gain tuning
ASIC Chip - Architecture
Mixed Signal ASIC
• RF, Analog & Digital
Blocks
IHP SG13S
• 130 nm SiGe technology
• High Performance BiCMOS
• npn BJT‘s fT /fmax = 250/300 GHz
• 3.7 V Breakdown Voltage
• 3.3 V CMOS
• 1.2 V Digital Library
ASIC Chip – Test Chip
Mixed Signal ASIC
• RF, Analog & Digital
Blocks
• Test Chip
IHP SG13S
• 130 nm SiGe technology
• High Performance BiCMOS
• npn BJT‘s fT /fmax = 250/300 GHz
• 3.7 V Breakdown Voltage
• 3.3 V CMOS
• 1.2 V Digital Library
RF Amplifier - Design
Design
• Cascode Amplifier
• Inductive Load
• Active Input Matching
• Active Output Matching
 Frequency 0.7– 2.3 GHz

 Gain > 18 dB
Bachmann [3]
 Gain Flatness < 2 dB

 Return Loss > 10 dB
 Output P1dB > 10 dBm
450μm
 OIP3 > 20 dBm
 Noise Figure < 6 dB
 DC Power < 300 mW 650μm
Bachmann [3]
RF Amplifier - Modelling PCB Losses
• Package
PCB
• QFN 9mm x 9mm
www.smartjac.biz [4]
• Packaged Chip mounted on PCB
• Model PCB Losses using CST Studio

Suite
Full Field EM Simulation using CST
CST Import Flow Simulation Setup-CST MWS
• Each trace – one discrete port at each end
• 28 ports in total
• Each port set to 50 ohms
• All materials– defined by their permittivity and conductivity
• Frequency Range: 0.5 GHz to 2.5 GHz
CST EM Simulation Results-I
Results for Amplifier Input Trace
CST EM Simulation Results-II
Results for Amplifier Output Trace
PCB traces cannot be considered lossless in the frequency

range of interest !!!
CST to Cadence Import
Cadence Import flow
• The N-port component acts
as an interface
N-port component
• It is basically a black box
• Uses an s-parameter file
• Can mimic any component

based on the s-parameter file
• Used to mimic the PCB traces
Co-Simulation in Cadence
Test Bench Setup in the Cadence

Environment
Co-simulation Results-I
Gain Comparison
• The figure shows how the gain
of the RF amplifier changes
• The PCB trace leads to gain

loss
• The maximum gain drops by

approx. 1.15 dB
Co-simulation Results-II
Scattering Parameter Comparison
Conclusion and Future Work
PCB
• Bond Wire Modeling
• QFN Package Modeling
• I/O Pad Modeling
• Combining and Testing
References
[1] Sreekesh Lakshminarayanan, “A Mixed-Signal ASIC for an RF Optical
Transceiver Module for FTTx Applications”, Analog Workshop 2016
[2] Finisar web portal, https://www.finisar.com/optical-transceivers/ftlf1619p1xcl
[3] Oliver Bachmann, “Design and Layout of an 0.7 GHz to 2.3 GHz, 18 dB Gain
and 10 dB Return Loss RF Amplifier”, Master Thesis, IES, TU Darmstadt
[4] http://www.smartjac.biz/webstore/oem/gem-serial-lite-pro-32-pin-qfn-chip-t-r
Thank you for
your attention!
QUESTIONS…?

Modeling The Impact of PCB Traces On The Performance of An RF Amplifier in An ASIC With The Help of CST-Studio Full Field EM Simulations and Cadence Virtuoso Co-Simulations

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Modeling The Impact of PCB Traces On The Performance of An RF Amplifier in An ASIC With The Help of CST-Studio Full Field EM Simulations and Cadence Virtuoso Co-Simulations

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Modeling the Impact of PCB traces on

the Performance of an RF Amplifier in an

Supervisor: Sreekesh Lakshminarayanan

• Introduction & Motivation

• RF Amplifier-Design & Modelling Losses

• Full Field EM Simulation using CST

• CST EM Simulation Results

• CST to Cadence Import

• Conclusion and Future Work

Central λ1λ2 λ3 λ4 … λN Passive

 Frequency 0.7– 2.3 GHz

 Gain Flatness < 2 dB

• Model PCB Losses using CST Studio

• Each trace – one discrete port at each end

• Each port set to 50 ohms

• All materials– defined by their permittivity and conductivity

• Frequency Range: 0.5 GHz to 2.5 GHz

Results for Amplifier Input Trace

Results for Amplifier Output Trace

PCB traces cannot be considered lossless in the frequency

• Uses an s-parameter file

• Can mimic any component

• Used to mimic the PCB traces

Test Bench Setup in the Cadence

• The PCB trace leads to gain

• The maximum gain drops by

• QFN Package Modeling

• I/O Pad Modeling

• Combining and Testing

[2] Finisar web portal, https://www.finisar.com/optical-transceivers/ftlf1619p1xcl

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