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Circuits: Introduction
Jun-Dong Cho
SungKyunKwan Univ.
Dept. of ECE, Vada Lab.
http://vada.skku.ac.kr
2
Contents
Why ASIC?
Introduction to System On Chip Design
Hardware and Software Co-design
Low Power ASIC Designs
Silicon in 2010
Density Access Time
Die Area: 2.5x2.5 cm (Gbits/cm2) (ns)
Voltage: 0.6 V DRAM 8.5 10
Technology: 0.07 m DRAM (Logic) 2.5 10
SRAM (Cache) 0.3 1.5
ASIC Principles
Value-added ASIC for huge volume opportunities;
standard parts for quick time to market applications
Economics of Design
Fast Prototyping, Low Volume
Custom Design, Labor Intensive, High Volume
CAD Tools Needed to Achieve the Design Strategies
System-level design: Concept to VHDL/C
Physical design VHDL/C to silicon, Timing closure
(Monterey, Magma, Synopsys, Cadence, Avant!)
Design Strategies: Hierarchy; Regularity; Modularity; Locality
ASIC Flow
Symbolic Layout
Process Migration - Retargeting Designs
Why SOC?
PC-Multimedia Applications
Physical gap
Timing closure problem: layout-driven logic and RT-level synthesis
Circular Y-Chart
performance
Power-hungry Applications
Software Behavioral
Functions Description
Power-driven Behavioral-Level
Processor Behavioral Power Analysis
Selection Transformation
Power Conscious
Behavioral
Description
To RT-Level Design
Gate-level
Description
Control and
Steering Logic RTL
Macrocells Switch-level
Description
structure
VLIW: Approach- flexible
Power-Down Techniques
◆ Lowering the
voltage along with the
clock actually alters
the energy-per-
operation of the
microprocessor,
reducing the energy
required to perform a
fixed amount of work
heterogeneity
Hardware/ software partitioning is “AI- complete”!
ASIP Design
Given a set of applications, determine micro architecture
of ASIP (i. e., configuration of functional units in
datapaths, instruction set)
To accurately evaluate performance of processor on a
given application need to compile the application
program onto the processor datapath and simulate object
code.
The micro architecture of the processor is a design
parameter!
Cross-Disciplinary nature