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Syllabus
Avionics system architecture Data buses MILSTD 1553 B ARINC 429 ARINC 629.
OSI Model Data unit Host Data layers Layer 7. Application 6. Presentation 5. Session Segment Media Packet layers Frame Bit 4. Transport 3. Network 2. Data Link 1. Physical Function Network process to application Data representation and encryption Interhost communication End-to-end connections and reliability Path determination and logical addressing Physical addressing Media, signal
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ACS
Types
I.
II.
Federated Architecture= Dedicated & independent processing and communication system with no Data Sharing eg. Arinc 429 and Saras of NAL Integrated Modular Architecture- A real time computer system with data sharing between Sensors and Effectors integrated to flight control, landing gear, display control. - 1553 A/B eg. Airbus & Arinc 629 (partially IMA & Fed)
Features -Federated
1. 2.
3.
4.
Stand-alone independent system with sensors, processing units and Effectors No Data Sharing between sensors, effectors and processing units Each system having own interfaces (CPU, I/O) to sensors and actuators (Effectors) Functions partitioned Eg. ARINC 429
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3. 4.
User interface = landing gear, processing unit, display and control Effector Used interface used for controlling the effector based upon feedback collected from a sensor Sensor 3 Units connected by dedicated communication channels.
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Features of IMA
1. 2.
3.
4.
5.
6. 7.
Sensor data shared between several systems In Core computer several modules identified performing a specific function like the flight control, landing gear, display control, etc. Multiple Federated application integrated into a single platform Strong Partitioning of Software & Two layer Software Architecture Inter partitioning of Communication Facility & Client Server inter partition Protocol Displaying of Status Messages Input/Output message handling by Message Handler and System Executive
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Advantages of IMA
Each Avionic Computer has Open System Interface called Application Program Interface API with Plug and Play Flexible communication having a logical channel and communication channel Flexibility in Hardware Architecture All LRM lightening protected,EMC and environmentally protected Fault Tolerance in IMA Full Duplex Switched Ethernet
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Disdvantages of IMA
Specific function for each LRM ( autopilot module, flight management module not interchangable) Modules not field replacable Multiple suppliers-not my problem
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2.
3. 4.
F22 Raptor Airbus 380 & Airbus A400 Boeing 787 Sukhoi Super Jet 100
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5.
Open System architecture with P&P Fully Duplex Only One Core Computer Field Replacable (LRM)except FM and Autopilot Highly fuel efficient and light weight
1.
2. 3. 4. 5.
Closed System architecture with no P& P Not Duplex Many Distributed Computers Not Field Replacable Poor Fuel efficient and Bulky.
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Aeronautical Standards
ARINC, 1553 1773
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Aeronautical Standards
ARINC-Aeronautical Radio IncorporatedArinc 400 series and Arinc 600,700 and 800 series, used by Boeing MIL Military, MIL 1553 standard Airbus
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ARINC 429
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ARINC-429
Unidirectional Bus operating at either 12.5 14.5 kbps or 100 kbps A Simplex Bus ( one TX and many Receivers) No Bus Controller, RT, or Bus Monitor contrary to 1553 ARINC use 32 Bit word with Odd Parity Waveform for ARINC is RTZ Bipolar
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31 32
0-32 bits for Arinc 429 1-8 bit for Label Bit 9 & 10 Station Identifier 11-29 for Data 30 & 31 bit =Sign and Status Bit Bit 32 for Parity
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2.
3. 4. 5.
419 453 in Inertial Navigation system 568 in Flight Recorder 619 629 used in Boeing 777
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ARINC 629
General Features,Protocol Layer,Timing Diagram (Periodic and Aperiodic) Comparison between 429 & 629
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2.
3. 4. 5. 6. 7.
8.
ARINC629- Multi transmitter to Multi receivers ARINC 629 = two independent MAC protocols for communications across a 20 Mbps Serial data bus High Speed Bi directional Bus (used in latest Boeing 777) ARINC 629- periodic and a-periodic transmissions 2 Protocols-Basic Protocol and Combined protocol; Basic protocol for flight controls, Combined protocol for flight management system No bus Controller required
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Protocol Layer-contd
Basic Protocol (DL):All transmissions fixed for periodic mode and individual transmissions vary for a-periodic modehave Terminal Gap, Synchronization gap
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CP
Transmitting both periodic and aperiodic Terminals transmit at periodic mode even if there is overload Terminals given equal opportunity to switch for overload
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0 for Parity
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Label Word
16 Bits assigned between Synchronization bits and parity bit- are Labels Synchronization bits to identify a Label Word Label bits numbered in reverse
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2.
3.
Transit timing condition T1- the moment the terminal starts transmittingT1 starts Synchronization gap-SG condition SG-starts the moment the terminal is quiet Terminal Gap condition TG-an unique timer assigned to the terminal; TG begins when SG is elapsed. TG & SG cannot overlap
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T1
TG2
T2
Tn
SG
Constant T1
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start
T2
Tn
Variable T1
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Parameter
Architecture Flow of Data
ARINC 429
On Federated Uni directional Simplex 32 bit in RTZ SP-MP Asynch.
ARINC 629
On IMA Bi Directional Duplex 20 bit word Basic & Combined MP-MP Sync & Async 2 Mbps Serial
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3 4
Transmission Speed
1553 B
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1553 B in an Aircraft
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1553 Architecture
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Architecture of 1553 B
Bus controller- the Master Device responsible for directing the flow of data into the bus 2) Remote Terminal-responsible for receiving the data and storing the data for flight test, maintenance and mission analysis 3) Bus Monitor-Responding to the commands addressed to Bus Monitor where 31 RT-s connected, but cannot transmit data
1)
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Architecture of 1553 B
B U S C O N Channel A Channel B
Remote Terminal 1
Remote Terminal 2
Remote Terminal 3
Bus Monitor
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Components of 1553 B
A dual-redundant MIL-STD-1553B bus A Bus Controller responsible for initiating message communication over the bus, detecting and correcting errors Three Remote Terminals Responsible for acquiring data from one Subsystem and transferring to another subsystem(eg, data from inertial navigation to cockpit display) A Bus Monitor-Responsible for monitoring all transactions over the bus and storing the data for later analysis, but does not transmit
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Components of 1553B
1.
2. 3.
4.
Encoder/Decodeer-input serial data using Manchestor coding with 12,16 or 24 Mhz clock Protocol Controller for message sequencing and error control CPU access the Block controller within the system Backend interface enabling the connection to a memory device
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1. 2. 3.
3 Types of Words in 1553 B of 20 bits with 3 bits for synchronization, 16 bits data and 1 bit for parity Command Word CW transmitted by BC Status Words SW transmitted by RT Data Word DW transmitted by BC or RT
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Sync
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Data One word=20 Bits
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Parity
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20 bit word Transmitted by Bus Controller of which (no BC address) 3 bits for sync using Manchestor coding 5 bits for address of RT 1bit Transmit/Receive (T/R) indicating data direction (T means Data recd by RT) 5 bits for sub address under RT address to memory etc 5 bit for data word count,indicating the word count after the sub address. 1 bit for parity check (using Odd parity)
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3 Sync
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RT Address
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T/R
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Sub address
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Data
1
Parity
Sync
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