Central Processing Unit

Contents
Introduction
General Register Organization Stack Organization

Instruction Formats
Addressing Mode Data Transfer and Manipulation

Program Control
Reduced Instruction Set Computer (RISC)
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Introduction

Major components of CPU

Register set

Control Arithmetic logic unit (ALU)

General Register Organization

Register set with common ALU

Clock

R1

Input

R2
R3 R4 R5 R6 R7 Load (7 lines) SELA

MUX

MUX

SELB

A bus
Arithmetic logic unit (ALU)

B bus

3X8 decoder
SELD

OPR

(a) Block diagram

Output

Examples of microoperations for the CPU

Microoperation

Symbolic designation SELA SELB SELD OPR

Control word

R1 R2 R3 R4 R4 V R5 R6 R6 + 1 R7 R1 Output R2 Output Input R4 shl R4 R5 0

R2 R4 R6 R1 R2 Input R4 R5

R3 R5 R5

R1 R4 R6 R7 None None R4 R5

SUB OR INCA TSFA TSFA TSFA SHLA XOR

010 100 110 001 010 000 100 101

011 101 000 000 000 000 000 101

001 100 110 111 000 000 100 101

00101 01010 00001 00000 00000 00000 11000 01100

Stack Organization

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Reverse polish Notation for stack

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Conversion RPN
Infix expression

(A+B)*[C*(D+E)+F] First perform the arithmetic inside the parenthesis. Next calculate the expression between the square brackets. The Multiplication must be done before in this C*(D+E)+F ,since multiplication has higher precedence over addition
RPN= AB+ DE+C*F+*
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Instruction Formats

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Instruction Format

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Addressing Mode

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ADDRESSING MODES

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 Implied Addressing mode: In this mode the operands are specified implicitly in the definition of

the instruction.
E.g. CMA ,CME because the operand in the accumulator register is

implied in the definition of the instruction.

Opcode

Mode

Address

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Immediate Addressing
Operand is part of instruction Operand = address field e.g. ADD 5
Add 5 to contents of accumulator 5 is operand

No memory reference to fetch data Fast Limited range

Opcode Instruction Operand

Direct Addressing
Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A
Add contents of cell A to accumulator Look in memory at address A for operand

Single memory reference to access data No additional calculations to work out effective address

Direct Addressing Diagram

Instruction Opcode Address A Memory

Operand

Indirect Addressing
Memory cell pointed to by address field contains the address of

(pointer to) the operand . EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator Multiple memory accesses to find operand Hence slower

Indirect Addressing Diagram

Instruction Opcode Address A

Memory
Pointer to operand

Operand

Register Addressing
Operand is held in register named in address filed

EA = R
Limited number of registers Very small address field needed
Shorter instructions

Faster instruction fetch

No memory access

Register Addressing Diagram

Instruction Opcode Register Address R Registers

Operand

Register Indirect Addressing

The instruction specifies the register which give the address of the

operand in the memory.

The selected register contain the address of the operand rather then

the operand itself.

The advantage of RIA mode is that the address field if the instruction

uses fewer bit to select the register then would have been required to specify the memory address directly.

Register Indirect Addressing Diagram

Instruction Opcode Register Address R Memory

Registers

Pointer to Operand

Operand

 Auto increment or Auto decrement Mode:

This mode is similar to register indirect mode except the register is incremented or decremented after (or before)its vale is accessed from the memory.

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Relative Addressing Mode:

In this mode the content of Program Counter (PC) is added to the address

part of the instruction in order to obtain the effective Address. E.g. Assume the PC=825 Address part of the Instruction contain 24 Then the instruction location 825 is read from memory during fetch phase and PC is incremented by 1. PC=825+1=826 Effective address=826+24=850 This mode is largely used in branch type instructions. It result in shorter address field in the instruction format since the relative address can be specified with the smaller no. of bits as compare to entire memory address.

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Indexed Addressing Mode:

In this mode the content of index register is added to

address part of the instruction to obtain the effective Address. Index register is a CPU register contain the index value. The address field of the instruction defines the beginning address of the data array in the memory. Each operand in the array is stored in the memory relative to the beginning address.

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Base Register Address Mode: The content of a base register is added to the address part of the instruction to obtain the effective address. This is similar to index register mode except the register is base register.

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Numerical example for addressing modes

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PROGRAM CONTROL
Instruction are stored in successive memory locations. When processed in

the CPU, the instructions are fetched from the memory place .
Program control types of instructions , when executed, may change the

address value of the program counter and causes the flow of instruction altered.
This change in program counter value result in execution of a program

control instruction causing break in sequence of instruction execution.

This is also known as Branching capability of digital system into various

segment of the program.

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Program Control

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Processor status word register

Status register is where the status bit condition can be

stored for further analysis. Status bits are also called condition code bit or flag bit. Common flags in PSW C, Carry is set to 1 if carry out of ALU is 1 S, Sign set to 1 if MSB bit is 1 Z ,zero is set to 1,if all the bits of output are 0s. V, Overflow set to 1,XOR of last two bits is equals to 1.
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Status register bits

A
8

B
8

C7

C8

8-bit ALU

C F7

F7~F0

Check for zero output

Output F

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CONDITIONAL BRANCH INSTRUCTIONS

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Reduced Instruction Set Computer (RISC)

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Introduction
The trend into computer hardware complexity was

influenced by various factors:

Upgrading existing models to provide more customer applications Adding instructions that facilitate the translation from high-level language

into machine language programs Striving to develop machines that move functions from software implementation into hardware implementation

A computer with a large number of instructions is

classified as a complex instruction set computer (CISC). A computer use fewer instructions with simple constructs so they can be executed much faster within the CPU without having to use memory as often. It is classified as a reduced instruction set computer (RISC).
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Introduction(cont.)
One reason for the trend to provide a complex instruction

set is the desire to simplify the compilation and improve the overall computer performance. The essential goal of a CISC architecture is to attempt to provide a single machine insruction for each statement that is written in a high-level language. Example of CISC architecture are the DEC VAX computer and the IBM 37 0computer.

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CISC characteristics
The major characteristics of CISC architecture are:
A large number of instructions typically from 100 to 250 instructions Some instructions that perform specialized tasks and are used

infrequently A large variety of addressing modestypically from 5 to 20 different modes Variable-length instruction formats Instructions that manipulate operands in memory

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RISC characteristics
The major characteristics of a RISC processor are:
Relatively few instructions Relatively few addressing modes Memory access limited to load and store instructions

All operations done within the registers of the CPU

Fixed-length, easily decoded instruction format Single-cycle instruction execution Hardwired rather than microprogrammed control

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RISC characteristics(cont.)
Other characteristics attributed to RISC architecture are:
A relatively large number of registers in the processor unit
Use of overlapped register windows to speed-up procedure call and return Efficient instruction pipeline Compiler support for efficient translation of high-level language programs

into machine language programs

Studies that show improved performance for RISC

architecture do not differentiate between the effects of the reduced instruction set and the effects of a large register file.
A large number of registers in the processing unit are sometimes associated

with RISC processors.

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Overlapped register windows

Some computers provide multiple-register banks, and each procedure

is allocated its own bank of registers. This eliminates the need for saving and restoring register values. Some computers use the memory stack to store the parameters that are needed by the procedure, but this required a memory access every time the stack is accessed. A characteristics of some RISC processors is their use of overlapped register windows to provide the passing of parameters and avoid the need for saving and restoring register values. The concept of overlapped register windows is illustrated in Fig. 8-9.

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Overlapped register windows(cont.)

In general, the organization of register windows will have

the following relationships:

number of global registers = G number of local registers in each window = L number of registers common to two windows = C number of windows = W

The number of registers available for each window is

calculated as followed:
window size = L + 2C + G

The total number of registers needed in the processor is

register file = (L + C)W + G

The example of Fig. 8-9:

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Overlapped register windows

R15 R10 R73 R64

Common to D and A
Local to D
R63 R58 R57 R48

Common to C and D Local to C

R47 R42

Proc D

Common to B and C
R41 R32

Proc C
R9 R0

Local to B
R31 R26

Common to all procedures

Common to A and B
R25 R16 R15

Proc B

Local to A Common to A and D

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Global registers

Proc A

R10

Berkeley RISC I
The Berkeley RISC I is a 32-bit integrated circuit CPU.
It supports 32-bit address and either 8-, 16-, or 32-bit data. It has a 32-bit instruction format and a total of 31 instructions. There are three basic addressing modes:

Register addressing, immediate operand, and relative to PC addressing for branch instructions. 10 global register and 8 windows of 32registers in each

It has a register file of 138 registers

The 32 registers in each window have an organization similar to the

one shown in Fig. 8-9.

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Berkeley RISC I(cont.)

Fig. 8-10 shows the 32-bit instruction formats used for

register-to-register instructions and memory access instructions. Seven of the bits in the operation code specify an operation, and the eighth bit indicates whether to update the status bits after an ALU operation. For register-to-register instructions :
The 5-bit Rd field select one of the 32 rgisters as a destination for the

result of the operation The operation is performed with the data specified in fields Rs and S2. Thus the instruction has a three-address format, but the second source may be either a register or an immediate operand.

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Berkeley RISC I(cont.)

For memory access instructions:
Rs to specify a 32-bit address in a register
S2 to specify an offset Register R0 contains all 0s, so it can be used in any field to specify a zero

quantity

The third instruction format combines the last three fields

to form a 19-bit relative address Y and is used primarily with the jump and call instructions.
The COND field replaces the Rd field for jump instructions and is used to

specify one of 16 possible branch conditions.

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Berkeley RISC I instruction formats

31 Opcode 8 31 Opcode 8 24 23 Rd 5 24 23 Rd 5 19 18 Rs 5 19 18 Rs 5 14 13 12 0 1 14 13 12 1 1 S2 13 Not used 8 54 S2 5 0 0

(a) Register mode: (S2 specifies a register)

(b) Register-immediate mode: (S2 specifies an operand )

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Opcode 8

24 23

19 18
COND 5 (c) PC relative mode: Y 19

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Instruction set of berkeley RISC I

The 31 instructions of RISC I are listed in Table8-12.
They have been grouped into three categories:
The data manipulation instructions:

Perform arithmetic, logic, and shift operations. An immediate operand is symbolized by the number sign #. ADD ADD ADD ADD ADD R22, R21, R23 R22, #150, R23 R0, R21, R22 R0, #150, R22 R22, #1, R22 R23 R22 + R21 R23 R22 + 150 R22 R21 (Move) R22 150 (Load immediate) R22 R22 + 1 (Increment)

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Instruction set of berkeley RISC I

The data transfer instructions:

Consist of six load instructions, three store instructions, and two instructions that transfer the program status word PSW. PSW contains the status of the CPU and includes the program counter, the status bits from the ALU, pointers used in conjunction with the register windows, and other info. That determine the state of the CPU.
LDL (R22)#150, R5 LDL (R22)#0, R5 LDL (R0)#500, R5 R5 M[R22] + 150 R5 M[R22] R5 M[500]

The program control instructions:

Operate with the program counter PC to control the program sequence One uses an index plus displacement addressing The second uses a relative to PC mode with the 19-bit Y value as the relative address

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Instruction set of berkeley RISC I

Opcode Operands Register transfer Description Data manipulation instructions
ADD ADDC SUB SUBC SUBR SUBCR AND OR XOR SLL SRL SRA Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rs,S2,Rd Rd Rs + S2 Rd Rs + S2 + carry Rd Rs - S2 Rd Rs - S2 - carry Rd S2 Rs Rd S2 Rs carry Rd Rs S2 Rd Rs V S2 Rd Rs S2 Rd Rs shifted by S2 Rd Rs shifted by S2 Rd Rs shifted by S2 Integer add Add with carry Integer subtract Subtract with carry Subtract reverse Subtract with carry AND OR Exclusive-OR Shift-left Shift-right logical Shift-right arithmetic

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Instruction set of berkeley RISC I(cont.)

Opcode Operands Register transfer Description

Data transfer instructions

LDL LDSU LDSS LDBU LDBS LDHI STL STS STB GETPSW PUTPSW (Rs)s2,Rd (Rs)s2,Rd (Rs)s2,Rd (Rs)s2,Rd (Rs)s2,Rd Rd,Y Rd,(Rs)S2 Rd,(Rs)S2 Rd,(Rs)S2 Rd Rd Rd M[Rs + S2] Rd M[Rs + S2] Rd M[Rs + S2] Rd M[Rs + S2] Rd M[Rs + S2] Rd Y M[Rs + S2] Rd M[Rs + S2] Rd M[Rs + S2] Rd Rd PSW PSW Rd Load long Load short unsigned Load short signed Load byte unsigned Load byte signed Load immediate high Store long Store short Store byte Load status word Set status word

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Instruction set of berkeley RISC I(cont.)

Opcode
JMP JMPR CALL CALLR RET CALLINT RETINT GTLPC

Operands
COND,S2(Rs) COND,Y Rd,S2(Rs) Rd,Y Rd,S2 Rd Rd,S2 Rd

Register transfer
PC Rs + S2 PC PC + Y Rd PC PC Rs + S2 CWP CWP 1 Rd PC PC PC + Y CWP CWP 1 PC Rd + S2 CWP CWP + 1 Rd PC CWP CWP 1 PC Rd + S2 CWP CWP + 1 Rd PC

Description
Conditional jump Jump relative Call subroutine and change window Call relative and change window Return and change window Disable interrupts Enable interrupt Get last PC
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Program control instructions

Homework # 4
Q8-36, Q8-37, Q8-39

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Data Transfer and Manipulation

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Typical data transfer instructions

Name Load Store Move Exchange Input Output Push Pop Mnemonic LD ST MOV XCH IN OUT PUSH POP

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Eight addressing modes for the load instruction

Mode Direct address Indirect address Relative address Immediate operand Index addressing Register Register indirect Autoincrement Assembly Convention LD ADR LD @ADR LD $ADR LD #NBR LD ADR(X) LD R1 LD (R1) LD (R1)+ Register transfer AC M[ADR] AC M[M[ADR]] AC M[PC + ADR] AC NBR AC M[ADR + XR] AC R1 AC M[R1] AC M[R1], R1 R1 + 1

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Typical arithmetic instructions

Name Mnemonic INC DEC ADD SUB MUL DIV SUBB NEG

Increment Decrement Add Subtract Multiply Divide Add with carry ADDC Subtract with borrow Negate (2s complement)

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Typical logical and bit manipulation instructions

Name Clear Complement AND OR Exclusive-OR Clear carry Set carry Complement carry Enable interrupt Disable interrupt Mnemonic CLR COM AND OR XOR CLRC SETC COMC EI DI

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Typical shift instructions

Name Logical shift right Logical shift left Arithmetic shift right Arithmetic shift left Rotate right Rotate left Rotate right through carry Rotate left through carry Mnemonic SHR SHL SHRA SHLA ROR ROL RORC ROLC

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