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Syllabus
Avionics system architecture Data buses MILSTD 1553 B ARINC 429 ARINC 629.
OSI Model Data unit Host Data layers Layer 7. Application 6. Presentation 5. Session Segment Media Packet layers Frame Bit 4. Transport 3. Network 2. Data Link 1. Physical Function Network process to application Data representation and encryption Interhost communication End-to-end connections and reliability Path determination and logical addressing Physical addressing Media, signal
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ACS
Types
I.
II.
Federated Architecture= Dedicated & independent processing and communication system with no Data Sharing eg. Arinc 429 and Saras of NAL Integrated Modular Architecture- A real time computer system with data sharing between Sensors and Effectors integrated to flight control, landing gear, display control. - 1553 A/B eg. Airbus & Arinc 629 (partially IMA & Fed)
Features -Federated
1. 2.
3.
4.
Stand-alone independent system with sensors, processing units and Effectors No Data Sharing between sensors, effectors and processing units Each system having own interfaces (CPU, I/O) to sensors and actuators (Effectors) Functions partitioned Eg. ARINC 429
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3. 4.
User interface = landing gear, processing unit, display and control Effector Used interface used for controlling the effector based upon feedback collected from a sensor Sensor 3 Units connected by dedicated communication channels.
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Features of IMA
1. 2.
3.
4.
5.
6. 7.
Sensor data shared between several systems In Core computer several modules identified performing a specific function like the flight control, landing gear, display control, etc. Multiple Federated application integrated into a single platform Strong Partitioning of Software & Two layer Software Architecture Inter partitioning of Communication Facility & Client Server inter partition Protocol Displaying of Status Messages Input/Output message handling by Message Handler and System Executive
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Advantages of IMA
Each Avionic Computer has Open System Interface called Application Program Interface API with Plug and Play Flexible communication having a logical channel and communication channel Flexibility in Hardware Architecture All LRM lightening protected,EMC and environmentally protected Fault Tolerance in IMA Full Duplex Switched Ethernet
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Disdvantages of IMA
Specific function for each LRM ( autopilot module, flight management module not interchangable) Modules not field replacable Multiple suppliers-not my problem
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2.
3. 4.
F22 Raptor Airbus 380 & Airbus A400 Boeing 787 Sukhoi Super Jet 100
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5.
Open System architecture with P&P Fully Duplex Only One Core Computer Field Replacable (LRM)except FM and Autopilot Highly fuel efficient and light weight
1.
2. 3. 4. 5.
Closed System architecture with no P& P Not Duplex Many Distributed Computers Not Field Replacable Poor Fuel efficient and Bulky.
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Aeronautical Standards
ARINC429,629 & 1553 1773
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Aeronautical Standards
ARINC-Aeronautical Radio IncorporatedArinc 429 series Arinc 629, used by Boeing MIL std Military, MIL 1553 standard Airbus
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ARINC 429
In brief,
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General
A physical and electrical interface of a two-wire data bus in most of the commercial and transport aircrafts One pair for TX and another pair for RX A data protocol to support an aircraft's avionics local area network. Use Star/Bus/Multiple bus topology
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ARINC 429
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In A NUTSHELL
Open Standard, with 32 bit word Transmission. A Simplex (TX & Rx on diff. ports) , Dedicated I/O with Point to Point, synchronous communication with 2 wire Operate on both discrete and analog signals Max 20 Receivers can be connected to the 2 wire. Sub Systems include FMS,ILS, VHF, Display system
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FEATURES
An Unidirectional Bus operating 12.5 or 14.5 or 100 kbps Use 32 Bit word with Odd Parity for error detection Waveform is RTZ bipolar It is Simplex Bus ,having RT, or Bus Monitor with no bus controller
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2.
3. 4.
429 Transmitter- 2 transmit channels 429 Receiver-20 incoming channels Software Interface Graphical user Interface GUI
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Word Format
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Word Format
32 BIT Format 1-8 for Label (for maintenance purpose) 9 & 10 for SDI ( Source Destination Identifier)-1 TX and 20 RX 11 to 29 Data both discrete and Numerical data 30 & 31 for SSM( Sign/Status Matrix) for reporting repair/fault on hardware status of en equiment 32 for Parity for error detection and correction.
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ARINC 629
General Features,Protocol Layer,Timing Diagram (Periodic and Aperiodic) Comparison between 429 & 629
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A Multipoint system- one transmitter to Multi receivers Has two independent MAC protocols for communications across a 2 Mbps Serial data bus Use High Speed Bi directional Bus Duplex Has periodic and a-periodic transmissions Has 2 Protocols-Basic Protocol and Combined protocol; Basic protocol for flight controls, Combined protocol for flight management system No bus Controller required
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2 2
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2.
3.
Transmitting only at aperiodic mode Normally Terminals transmit on periodic mode on no overload Even if there is overload, it is transmitting on aperiodic mode
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CP
Transmitting both periodic and aperiodic Terminals transmit at periodic mode even if there is overload Terminals given equal opportunity to switch for overload
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Timers used
1.
2.
3. 4.
Timer 1 for Transmit Internal T1 Timer 2 for Synchronisation Gap SG Timer 3 for Terminal Gap TG These 3 timers work both on Periodic and Aperiodic mode
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Timing Status
1.
2.
3.
TG-Terminal Gap An unique timer assigned to the terminal for waiting after a bus activity. TG begins when SG is elapsed. SG-Synchronization gap- A quiet time condition SG-starts the moment the terminal is quiet; TG & SG cannot overlap;SG starts when the bus is quiet. Transit timing condition T1- Transmit Timer starts the moment the terminal starts transmitting51
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TG
SG
T1
TG2
T2
Tn
SG
Constant T1
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T1
T2
Tn
stop
Variable T1
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Word Format
1.
20 bit word using CSMA/CA protocol 16 Bit Data Word; 16 Bits assigned between Synchronization bits and parity bit- are Labels 1 Bit for Parity 3 Bit for Synchronization HI to LO
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0 for Parity
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Parameter
Architecture Data Flow
ARINC 429
ARINC 629
3 4 5
Federated F + IMA Uni Bi Directional directional Duplex Simplex 32 bit in RTZ 20 bit word P-P P-MP Asynch. Sync & Async 12.5 Kbps to 2 Mbps Serial 100 kbps
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1553 B
Salient features, A and B, Data Encoding, Architecture, Components, Word format
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Features
1. 2. 3. 4. 5. 6. 7. 8.
A Serial dual redundant Duplex bus on 1 Mbps Manchestor Data Encoding 16 Bit word Size Data Modulation by PCM Using both Twisted Pair and Transformer for coupling BC,RT & BM connected to the bus, RT-stand alone Unit Can connect 31 RT-s remote terminals
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Architecture of 1553B
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Architecture of 1553 B
B U S C O N Channel A Channel B
Remote Terminal 1
Remote Terminal 2
Remote Terminal 3
Bus Monitor
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Remote Terminal
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Remote Terminal
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Bus controller
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Bus Monitor
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Architecture
A dual-redundant bus 2. A Bus Controller responsible for communication over the bus, and for detecting and correcting errors 3. 3 Remote Terminals Responsible for acquiring data from one Subsystem and transferring to another subsystem 4. A Bus Monitor-For monitoring all transactions over the bus and storing the data.BM does not transmit
1.
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Bus controller- responsible for directing the flow of data into the bus Remote Terminal-responsible for receiving the data and storing the data Bus Monitor-Responding to the commands addressed to Bus Monitor where 31 RT-s connected, but cannot transmit data
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1553 In field
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Bus Controller
Supporting 128 kBytes memory Synchronous or Asynchronous interface Clock rate 12, 14, 16 or 24 MHz Verilog Source Code Use Ma nchestor Encoding
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Word format
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2.
3.
3 Types of Words-CW,SW and DW in 1553 B Word Size 20 bits 3 bits for synchronization, 16 bits data and 1 bit for parity Command Word CW transmitted by BC Status Words SW transmitted by RT Data Word DW transmitted by BC or RT
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BC to RT -Bus Controller to Remote Terminal RT to BC Remote Terminal to Bus Controller RT to RT-Remote Terminal to Remote Terminal
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Status Word-RT to RT
Transmitted by RT from BC 3 bit-time sync pattern (same as for a command word) 16 bits for Data in Status 1 parity check bit.
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3
Sync
16
Data One word=20 Bits
1
Parity
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Command Word-BC to RT
20 bit word Transmitted by Bus Controller of which (no BC address) 3 bits for sync using Manchestor coding 5 bits for address of RT 1bit Transmit/Receive (T/R) indicating data direction (T means Data recd by RT) 5 bits for sub address under RT address to memory etc 5 bit for data word count,indicating the word count after the sub address. 1 bit for parity check (using Odd parity)
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3 Sync
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RT Address
1
T/R
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Sub address
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Data Word RT to BC
20 bit Data Word transmitted by RT or BC against a BC request 3 bits for sync pattern (opposite in polarity from command and status words) 16 bit for data field 1 bit for parity check bit.
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16
Data
1
Parity
Sync
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2.
3. 4. 5.
00000 Dynamic Bus Control 00001 or 10000 Synchronise 00010 Transmit Status 00100 Transmit Shut down 01000 Reset Remote Terminal
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1
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Architecture
Signal Format and Parity Data Bus Terminals Coupling
Data System & speed
IMA
Manchestor Odd
3RT, One BC &BM STP &Transformer
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4 5
Multiplex 1 Mbps
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