DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name of the faculty : M. HEMALATHA
Designation : Lecturer
Branch : ECE
Topic : Sequential Logic Circuits
Year/semester : III semester
Subject : Digital electronics
Subject code : EC 304
Duration : 100 min.
Sub-topic : Pre-set and Clear Inputs, Race
around condition, Master slave
JK Flip-Flop, D,T Flip-Flops
Teaching aids : PPTs

EC304.37 TO 38 1
OBJECTIVES

On the completion of this period, you would be able

to

• Understand Preset and clear inputs.

• Race around condition.

• Master slave JK Flip-flop.

• D, T Flip-flops.

EC304.37 TO 38 2
Recap

(1) What is flip- flop?

(2) Types of flip – flop.

(3) RS flip- flop.

(4) Clocked RS flip- flop.

EC304.37 TO 38 3
PRESET AND CLEAR INPUTS
• The JK Flip-flop with preset and clear inputs is as
shown in the figure.

Fig 1
EC304.37 TO 38 4
Fig 2
Table 1

EC304.37 TO 38 5
PRESET AND CLEAR INPUTS (contd.)

• The preset and clear data are called direct or

asynchronus inputs.

• These inputs are not in synchronism with the clock.

• May be applied at anytime in between clock pulses.

EC304.37 TO 38 6
PRESET AND CLEAR INPUTS (contd.)

• The output of Flip-flop is set to 1 by

activating the preset input

•The output of Flip-flop is reset to 0 by

activating the clear input

EC304.37 TO 38 7
RACE AROUND CONDITION
• In JK Flip-Flop ,if J=1, K=1, Q=0, and when the Clock
pulse is applied then Q=1 .This change takes place after
time interval, Δt.

• Δt= propagation delay.

• Now J=1 K=1 Q=1 and if the clock pulse is still present ,Q
changes back to 0.

• So for the duration tp of clock pulse the output will

oscillate between 0 and 1.

EC304.37 TO 38 8
RACE AROUND CONDITION (Contd)

• Output Q is ambiguous. This situation is race-around

condition.

• Race-around condition is avoided if tp < Δt.

• Master slave JKFF is introduced to solve this problem.

EC304.37 TO 38 9
MASTER SLAVE JKFF
• Avoids race around condition problem.

• Logic diagram as shown in the figure

Fig 3

EC304.37 TO 38 10
CLOCKED MASTER SLAVE JK FLIP-FLOP

Fig 4
EC304.37 TO 38 11
 Table 2
EC304.37 TO 38 12
Timing diagram of master-slave JK Flipflop

Table 2
EC304.37 TO 38 13
• When the clock is HIGH, the master is active.

• Clock is HIGH, SLAVE is inactive and its output

remains in previous state.

• Clock is low, MASTER is inactive and SLAVE is

active.

EC304.37 TO 38 14
D(DELAY) FLIPFLOP

• D FF has only one input.

• Used for storing the information.

• The output Q follows the input D after one clock pulse only.

• Output Q=D

EC304.37 TO 38 15
D (DELAY) FLIPFLOP

Fig 6

EC304.37 TO 38 16
D (DELAY) FLIPFLOP

Fig 7

EC304.37 TO 38 17
D (DELAY) FLIPFLOP

Table 3

EC304.37 TO 38 18
D(DELAY) FLIPFLOP

Fig 8

EC304.37 TO 38 19
T-flip-flops

• When T=0 is applied Qn+1=Qn

• When T=1 is applies Qn+1= Qn

EC304.37 TO 38 20
T FLIPFLOP(TOGGLE FF)

Fig 9

EC304.37 TO 38 21
T FLIPFLOP(TOGGLE FF)

Fig 10
Table 3

EC304.37 TO 38 22
T FLIPFLOP(TOGGLE FF)

Fig 11

EC304.37 TO 38 23
Quiz

1. The flip-flop which eliminates the racing condition

effectively

a) RS flip-flop

b) D-flip-flop

c) T flip-flop

d) JK-flop-flop

EC304.37 TO 38 24
2. The preset and clear data inputs are also called as

inputs

a) Synchronous

b) Asynchronous

c) Both

d) None

EC304.37 TO 38 25
SUMMARY

• We have discussed about

• Preset and clear inputs.

•.Race around condition.

• Master-Slave JK Flipflop.

• D and T Flipflops.

EC304.37 TO 38 26
Frequently Asked Questions

• Draw the logic diagram of a JK flip-flop with preset

and clear inputs and explain.

• Draw the logic diagram of a master slave JK flip-flop

and explain with a neat timing diagram and truth
table.

• Explain the conversion of JK flip-flop into T flip-flop.

EC304.37 TO 38 27