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Timing diagram
Address Bus, R/W, Data Memory Map I/O
Address Decoding
CPU is addressable lager than devices.
Chip Supports
TTL : De-multiplexer, Latch, Buffer
Basic Architecture
Bus Architecture
Address:
If I/O, a value between 0000H and FFFFH is issued. If memory, it depends on the architecture:
20 24 25 32 36
Bus Architecture
Data:
8 -bits (8088) 16 -bits (8086/80286/80386SX/SL/SLC/EX) 32 -bits (80386DX/80486/Pentium) 64 -bits (Pentium/Pro/II/III)
Control:
Most systems have at least 4 control bus connections (active low). MRDC (Memory ReaD Control), MWRC , IORC (I/O Read Control), IOWC
Bus Standards
EISA : 8 MHz
32-bit (older 386 and 486 machines).
Bus Standards
IEEE 1394
400 Mbps, primary target is audio/visual consumer electronic devices
IO Space
MEMORY
Memory Types
Memory Chips
Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) pin that enables the memory device.
This enables read and/or write operations. If more than one are present, then all must be 0 in order to perform a read or write.
SRAMs
SRAMs used for caches have access times as low as 10ns .
DRAMs
SRAMs are limited in size (up to about 128Kb). DRAMs are available in much larger sizes, e.g., 64M X 1. DRAMs MUST be refreshed every 2 to 4 ms Since they store their value on an integrated capacitor that loses charge over time.
This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used. Rather the 3-to-8 Line Decoder (74LS138) is more common.
G2A, G2B, and G1 must be active. Each output of the decoder can be attached to an 2764 EPROM ( 8K X 8 ).
EPROM 2764 x 8
A PAL example (16L8) is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above.
AMD 16L8 PAL decoder. It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that can be either (Pins 13-18).
The 8088 runs at 5MHz and only allows 460ns for memory to access data. A wait state adds 200ns of additional time
The 62256s on the previous slide are actually SRAMs. Access times are on order of 10ns . Flash memory can also be interfaced to the 8088. However, the write time ( 400ms !) is too slow to be used as RAM.
PPI : 82C55
The 82C55 is a popular interfacing component, that can interface any TTL-compatible I/O device to the microprocessor. It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset). Requires insertion of wait states if used with a microprocessor using higher that an 8 MHz clock. PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of operation. In the PC, an 82C55 or its equivalent is decoded at I/O ports 60H-63H.
Thats all