Professional Documents
Culture Documents
edu
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Overview
y What is CISC and Why to learn? y History y Architecture
y Typical x86 design y Characteristics & Addressing modes
y CISC Vs RISC
y Example Programs
y The Performance Equation y FAQs y Recent Developments & Future Scope y Resources y Questions
4/28/2008 Computer Architecture & Design (6200) Class Presentation 2
What is CISC?
y Definition: Pronounced "sisk" and standing for Complex Instruction Set Computer, is a Microprocessor Architecture that aims at achieving complex operations with single instructions and favors the richness of the instruction set (typically as many as 200 unique instructions) over the speed with which individual instructions are executed.
History
Generation 1 (IA-16) 2 First introduced 1978 1982 Prominent Consumer CPU linear / physical address brands space Intel 8086, Intel 8088 Intel 80186, Intel 80188, NEC V20 Intel 80286 Intel386, AMD Am386 Notable (new) features 16-bit / 20-bit (segmented) first x86 microprocessors see above hardware for fast address calculations, fast mul/div etc
2 3 (IA-32)
1982 1985
16-bit (30-bit virtual) / 24- MMU, for protected mode bit (segmented) and a larger address space 32-bit (46-bit virtual) / 32- 32-bit instruction set, bit MMU with paging see above RISC-like pipelining, integrated FPU, on-chip cache superscalar, 64-bit databus, faster FPU, MMX register renaming, speculative execution
1989
Intel486
5 5/6
1993 1996
1995
-op translation, PAE (not see above / 36-bit physical K5), integrated L2 cache (PAE) (not K5)
Continued .
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Continued .
Generation 6 7
Prominent Consumer CPU linear / physical address brands space AMD K6/-2/3, Pentium see above II/III Athlon, Athlon XP see above
Notable (new) features L3-cache support, 3D Now, SSE superscalar FPU, wide design (up to three x86 instr./clock) deeply pipelined, high frequency, SSE2, hyperthreading optimized for low power x86-64 instruction set, ondie memory controller very deeply pipelined, very high frequency, SSE3 low power, multi-core, lower clock frequency monolithic quad-core, 128 bit FPUs, SSE4a Hyper Transport 3, native memory controller, on-die L3 cache
7 6/7-M 8 (x86-64) 8 9
see above see above 64-bit / 40-bit physical in first impl. see above see above (some are 32bit only)
10
2007-2008
AMD Phenom
see above
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Architecture
A typical x86 Architecture
Characteristics
o o o o CISC are Mostly Von Neumann Architecture (There are few exceptions) Same bus for program memory, data memory, I/O, registers, etc Generally Micro-coded ,Variable length instructions Segmentation is possible with Segment Register s like DS, ES and an offset which can be common to all segments. o Many powerful instructions are supported, making the assembly language programmer s job much easier. o Physical Memory Extension Possible
Addressing modes
o o o o o o o Register Addressing Mode Memory Addressing Modes Displacement Only Addressing Mode Register Indirect Addressing Modes Indexed Addressing Modes Based Indexed Addressing Modes Based Indexed Plus Displacement Addressing
Computer Architecture & Design (6200) Class Presentation 7
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CISC Vs RISC
Example Program
Main Memory
ALU
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Operands: M[2:3] = operand 1 (15) M[5:2] = operand 2(20) Task : Multiplication Result: M[2:3] <= result
Computer Architecture & Design (6200) Class Presentation
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Loads the two operands into separate registers Multiplies the operands in the execution unit Then stores the product in the some temporary register Stores value back to memory location 2:3
MULT is what is known as a "complex instruction." Operates directly on the computer's memory banks Does not require the programmer to explicitly call any loading or storing functions. closely resembles a command in a higher level language. e.g. a C statement "a = a * b."
4/28/2008 Computer Architecture & Design (6200) Class Presentation 10
LW LW MULT SW
2. 3. 4.
Load operand1 into register A Load operand2 into register B Multiply the operands in the execution unit and store result in A Store value of A back to memory location 2:3
These set of Instructions is known as a Reduced Instructions." Cannot Operate directly on the computer's memory banks Requires the programmer to explicitly call any loading or storing functions. RISC processors only use simple instructions that can be executed within one clock cycle
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CISC
y Primary goal is to complete a
RISC
y Primary goal is to speedup
y y y
y y y
task in as few lines of assembly as possible Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes High cycles per second Variable length Instructions
individual instruction
y y y
reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Large code sizes Low cycles per second Equal length instructions which make pipelining possible
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1 The CISC approach minimizes the number of instructions per program (2) sacrificing the number of cycles per instruction. (1) RISC does the opposite reduces the cycles per instruction (1) sacrificing number of instructions per program (2)
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FAQs
Which one is faster?
Well, it is commonly accepted that RISC ISA's should make computers faster. The main reason why is because RISC computers figure out more words in a shorter amount of time due to pipelining.
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IA-64
What is IA-64?
IA-64 is a new instruction set architecture. IA-64 seeks to address: branch delays and memory latency.
IA-64 Realities:
"A study in ISCA '95 by S. Malhlke, et. al. demonstrated that predication removed over 50% of the branches and 40% of the mis-predicted branches from several popular benchmark programs." ( http://www.hp.com/esy/technology/ia_64/products/isapress.html ) IA-64 lack compatibility with Intel x86 and HP PA-RISC architectures, so this additional compatibility logic will take lot of die space. Presently, the compilers are in experiment phase and IA-64 has no OS support.
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Resources
o http://www.pctechguide.com/glossary/WordFind.php?wordInput=CISC o http://www.cs.umd.edu/class/fall2001/cmsc411/projects/IA64/ o http://cse.stanford.edu/class/sophomore-college/projects00/risc/risccisc/index.html o http://en.wikipedia.org/wiki/Complex_instruction_set_computer o http://en.wikipedia.org/wiki/X86 o http://arstechnica.com/cpu/4q99/risc-cisc/rvc-6.html
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Questions ??
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