TIMING ISSUES

Presented By Gaurav

Timing Issues


What we know  A lot of logic synthesis, going from a specification to a gate- level design.  How to simulate a design and verify what it does. What we don t know  Verifying timing behavior of synthesized object.  We have a gate- level netlist,  We have timing models of the gates and maybe wires too,  Now, what we have to do with it;  To know, When signals arrive at various points in the network, or  Which are the Longest and shortest delays through gate network, or  Does our design (netlist) meet some timing requirement ?

Timing Issues


Basic Questions  Does my design meet a given timing requirement, or  How fast I can run the design ?  Are there any chances of failures ? We have discussed nominal delay simulation; why not use it..?  Requires too many patterns.  Increases exponentially with the number of design inputs.  Even worse if we consider sequences needed to initialize latches. So what we do instead..??  Separate function from time,  Determine when transitions occur without worrying about how.

Timing Issues
 

  

So, basic idea of Static Timing Analysis is, Instead of considering an infinitely long simulation sequence, fold all possible transitions back into a single clock cycle. Assume that signal becomes stable at latest possible time. Assume signal becomes unstable at the earliest possible time. If the design works at these extremes, we can guarantee it always will . Static part just means we aren t doing simulation (dynamic).

Terminologies
         

Flow Diagram Clock Gated Clock Set-up and Hold times Asynchronous I/Ps and Metastability Clock Skew Timing Issues Constraints Static Timing Analysis Dynamic Timing Analysis

Design Flow
Specifications

Test Bench

Functional Simulation Pre-Layout Simulation

Design Entry

Synth. Lib
Logic Synthesis Static Timing Analysis

Constraints Timing Lib.

System partitioning and Floor-planning Post-Layout Simulation Placement and Routing Physical Verification Fab proto type and Testing Production

Timing Analysis Flow

Design Data base Parasitic Extraction Wire Resistance and Capacitance

Slew Rates

Delay calc.

Static Timing Analysis Time windows Timing Report Timing Constraints NO Timing Library

Timing ok Yes

Go back to RTL coding

Sign Off

Clock


Clocks  Are signals with a periodic behavior. In synchronous circuit designs, clocks are used to synchronize the propagation of data signals by controlling sequential elements. Minimum Pulse Width Is necessary to ensure that sequential devices are clocked correctly.  If pulse width is too small a sequential device may not recognize the clock.

Gated Clock


Disadvantages of gated clock:  Results in glitches. (unwanted short pulses)  Latches unwanted spurious data. Tradeoff:  Gating of clock reduces power consumption.

Set-up and Hold times

 

Set-up time  Is defined as the minimum length of time that a data input pin must be stable before the active clock transition. Hold time  Is defined as the minimum length of time that a data input pin must be stable after the active clock transition.

tsu thd Stable

D changing
Assuming F/Fs are +ve edge triggered.

D changing

Asynchronous inputs
 

Not all inputs are synchronized with the clock Examples:  Keystrokes  Sensor inputs  Data received from a network (transmitter has its own clock) Inputs must be synchronized with the system clock before applying to a synchronous system.

Is there any problems in doing this? Yes.! The timing requirements of an F/F can be violated.

Metastability


Set-up or Hold time violation leads to Metastability. Meta- In Between Stable Is a condition in which the response of a flip-flop to an asynchronous input is undetermined.  Because, asynchronous data inputs to a clocked flip-flop can cause Set-up or Hold time violations. A metastable flip-flop will appear, as a Flip-flop that switches late or doesn t switch at all. This flip-flop can present a brief pulse at the output or cause flip-flop output oscillations, and hence system failures.

Another look at Metastability



 

As we know that the violation of setup or hold time will lead to Metastability. And we should also be aware that what is happening at the o/p. A F/F has two stable states, logic- 0 and logic 1 , then what exactly is meant by metastable state.

Metastability


MTBF ( Meantime between failure) can be calculated using the following formula:  with fin : Data rate at D-input  fCLK : Clock frequency  td : Critical Time window

Ex. : Data is transmitted in frames so that if you break it before 33.3s correct data transmission is assured.

Use Synchronizer

What to Do?


Dual Rank Synchronizer

What to Do?


Dual-Rank Synchronizer :  Two flip-flops are connected together as a Shift-register.  Three situations can occur when Flip-flop 1 is in metastable state.  The metastable state of the first Flip-flop is short enough, so at the next rising edge of the clock signal the second flip-flop already gets a good signal at its D-input.  The metastable state of the first flip-flop lasts longer than one clock period, but the second flip-flop accepts the undefined signal as a valid high or low state.  The metastable state of the first flip-flop lasts longer than one clock period and the second flip-flop becomes metastable, too. In the first two cases the output of the second flip-flop is not metastable, while the last one is metastable. This shows the reduction of metastable states with this circuit.

Clock Skew
 

Clock Skew  Is defined as the difference in the arrival time of clock edges at one or more register clock pins. Positive clock Skew : Source register is clocked earlier than the destination register Negative clock Skew : Destination register is clocked earlier than the source register.

RTL Diagram
Tcq
I/P D Q Tsu Th O/P

Tcom

FF1

FF1

CLK

Tsk

STA- No Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2

LAUNCH CLOCK = CAPTURE CLOCK as no SKEW

Tmin = Tcq + Tcom + Tsu F = 1 / Tmin

Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2 SKEW CAPTURE CLOCK with SKEW

Tmin = Tcq + Tcom + Tsu Tsk F = 1 / Tmin

More Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2 SKEW CAPTURE CLOCK with SKEW

Tmin = Tcq + Tcom + Tsu - Tsk F = 1 / Tmin

More Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2 SKEW CAPTURE CLOCK with SKEW

Tmin = Tcq + Tcom + Tsu - Tsk F = 1 / Tmin

More Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2 SKEW CAPTURE CLOCK with SKEW

Tmin = Tcq + Tcom + Tsu - Tsk F = 1 / Tmin

More Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2 SKEW CAPTURE CLOCK with SKEW

Tmin = Tcq + Tcom + Tsu - Tsk F = 1 / Tmin

Max Skew
LE1 LAUNCH

Tcq T=0

Tcom

Tsu

Th
Capture Any Time Here After

CE1 Capture Edge Tmin CE2 SKEW CAPTURE CLOCK with SKEW with CAPTURE CLOCK SKEW

NOTICE

Tmin = Tcq + Tcom + Tsu Tsk while Tmin > Th F = 1 / Tmin

Clock Tree
 

Clock signal has the maximum number of Loads [connections] Clock net is the most power hungry net on the chip. .. Why??? Hence, defining the clock is an important aspect for high speed chip designs. Need - Clock Skew should be minimum [ ideally zero ] at all clock loads. Therefore all devices [ ASICs and PLD s] have special schemes for the clock net.

Clocks - Are Power Hungry

P = F.C.Vdd 2
Not Only the Clock Capacitance is large, it switches every cycle.

Clock Tree


Clock Tree


Places clock and clock buffers at proper points. Develops interconnect geometry connecting CLK to inputs of all sequential devices on the chip.

H-Tree network:


Types of Clock Trees

Suitable for regular array network. Delay for each sub-block is equal. The sub-block should be small, so that the skew within the block is tolerable.

Hierarchical Tree Network:



Types of Clock Trees

Intermediate buffer is to isolate local clock nets from upstream load impedance and to amplify the clock signals degraded by RC nets. Number of intermediate buffers depends on interconnect materials, size and fan-out of the clock network.

Timing Issues


Timing Paths Path Groups Path Delays

Timing Paths


Timing analysis is performed by splitting the design into different paths based on
 

Start points End points

Start points comprise of :



Input ports and clock pin of a sequential element.

End points comprise of :



Output port and data pin of a sequential element.

Timing Path Analysis is done between a start

Timing Paths


Timing Paths  Are paths carrying information regarding the timing behavior of signal flow, from one timing group (called the starting group ) to another timing group (called the ending group ).

Timing Paths


Clock to Setup Path  Is the time required for data to propagate through source flip-flop, travel through logic and routing, and arrive at the destination before the next clock edge occurs.
A Q D

Clk

Timing Paths


Clock to Pad Path  Is the time required for data to leave source flip-flop, travel through logic and routing, and leave the chip.
A Q D

Clk

Timing Paths


Paths ending at Clock pin of Flip-flops :



Time required for signal to arrive at flip-flop clock input. Propagates through any number of levels of combinatorial logic and ends at any clock pin on a flip-flop or latch enable.
D En Clk Q

Timing paths


Pad to Pad Path :  Starts at an input pad of chip.  Propagates through one or more levels of combinatorial logic.  Ends at output pad of chip.  Is not controlled or affected by any clock signal.

A B A B Y D Q

Clk

Timing Paths


Pad to Setup Path :



Starts at an input pad of the chip, propagates through one or more levels of combinatorial logic, and ends at the input of Flip-flop.
A B Clk Q

Determine the timing paths ???

False Path


False Paths  Are logic paths which are never exercised by a design in its normal functional operation.  Synthesis spends more time on optimizing the unwanted part of the logic when False path is not specified. Ex. : Scan multiplexer

Path Groups


Path groups is a collection of sequential elements and ports that have common timing behaviour.
 

Example All inputs, outputs, flip-flops or latches are clocked by the same clock.

Default path group comprises all paths not associated with a clock.

Determine the Path Groups???

Off - Chip Delays



Two kinds of off-chip delays

 

Input delay Output delay

Have to be declared external to the synthesis environment. Need :



An independent module may work fine under isolated conditions but may not work when connected together with other modules.

Off-chip Delays

Calculate the I/O Delays



Maximum and minimum values of these delays must be termed to take care of the uncertainty.

Timing Issues n
k-bit Present State Value
k Combinational Logic Circuit DFF Q D k

k-bit Next State Value

clk

Question: What is the MAXIMUM frequency of operation of this system? Maximum Frequency = 1/ (longest delay path I.e. Critical Path)

Reg to Reg delay

Very often, all inputs and outputs are registered. Then register-toregister delay will almost always determine maximum frequency. Tsetup

D N C Q N

Combinational Logic Tpd max

D K C Q K

C2Q
delay = Tc to q + Tpd max + Tsetup; Thd<= Tclkperiod

Latency and Throughput

Length L objects moves at rate R objects / minute.

Latency : Time for one object to pass through the system is L/R. Throughput : Rate of objects going through.

Latency and Throughput

Latency and Throughput

Latency and Throughput

 

For faster throughput, the designer splits up the logic so that fewer operations appear between two clock edges. Functionally the designs are the same but the designs will have greater latency and will operate at a higher clock rate. Higher frequencies can be achieved by pipelining to reduce the amount of logic that must resolve in a clock cycle. Latency :  Is the total number of clock cycles required to execute all operations in a single loop iteration. Throughput :  Is defined as the rate at which a system can sample new data for processing. Pipelining :  Is the process of adding registers to meet clock timing requirements at the expense of a slower Latency.

Setup, Hold Time for External Inputs

External inputs are buffered through pad drivers and may go through combinational logic before they reach a synchronous input. This buffering adds propagation delay. How does this propagation delay affect the EXTERNAL setup and hold time ?? ASIC Tsu, Thd DIN
Thd, Tsu(ext) Combo
D Q

CLK

External Setup & Hold Time ASIC

Tsu, Thd DIN
Thd, Tsu(ext) Combo
D Q

CLK

Worst case setup time for DIN occurs when DIN is DELAYED relative to CLK. Means clock edge arrives early, requiring DIN to be ready sooner. Din Setup = Tsu + Tpd DIN (max) - Tpd CLK (min). Worst case hold time for DIN occurs when CLK is DELAYED relative to DIN. Means clock edge arrives late, requiring DIN to hold its value longer. Din Hold = Thd + Tpd CLK (max) - Tpd DIN (min).

Timing Issues Skew

Positive Clock

Some positive skew can be beneficial, it will decrease the required Setup time. Too Much positive skew can create a race condition, Hold-time violation.
Clock @ Source Register Clock @ Destination Register

Clock @ Source Register Clock @ Destination Register

Jitter


Clock network delay uncertainty



 

From one clock cycle to the next, the period is not exactly the same each time. Maximum difference in phase of clock between any two periods is jitter. So Jitter, J1 = T2 - T 2 and J2 = T3 - T 3

Jitter


Caused by variations in clock period that result from:  Phased- lock loop (PLL) oscillation frequency.  Various noise sources affecting clock generation and distribution. Ex. Power supply noise which dynamically alters the drive strength of intermediate buffer stages.
Vdd Vout Vin Noise

Jitter
 

Needs to be considered in maximum path timing (setup). Typically on the order of 50ps in high- end microprocessors.

Desired critical window Jittered critical window

Setup Violation

Slack

Slack
 

Slack is the difference between,  Desired time and actual / achieved time [ for a timing path ]. Slack Time determines [ for a timing path ], if the design is working at the specified Speed / Frequency. Positive Slack means, design is working at specified frequency and still has some margin. Zero Slack means, design is critically working at the specified frequency and there is no margin. Negative Slack means, design does not achieve the specified timings at specified frequency. Slack has to be positive always and negative slack indicates a violation in the Timing

Constraints
 

Input parameters called Constraints are given to Tools to achieve design goals. Constraints are of 2 - types Area Constraints and Speed Constraints.  Area Is a unit of the complexity ( I.e. size ) of a design. It is measured generally in, number of transistors ( i.e Gates), and sometimes in square mils.


Speed Is defined as the maximum operating frequency. Timing constraints play a key role in specifying the maximum speed of a design.

Static Timing Analysis

 

STA is a synthesis issue. Synthesis of a design is the process of converting the design into a gate level schematic. Conversion of a design to gate level schematic depends upon the timing constraints given. e.g. From the above e.g. it is clear that synthesis is timing constraint driven.

Static Timing Analysis



Therefore STA is an inbuilt process inside a synthesis tool,  To break the design into sets of timing paths.  Where delay of each path is calculated.  And all path delays are checked to see if timing constraints are met. That means  Synthesis tools, have in them a Timing Analysis Tool (Static Timing Analyzer) which helps them in optimizing logic.  Unlike simulation STA does not require any external input signals.  STA analyzes the design for all timing paths.  STA helps synthesizer to optimize the design, till it meets the timing constraints.

Dynamic Timing Analysis



DTA is a simulation issue. Simulation of a design is the process of checking the functionality of the design. DTA simulates the design at the operating frequency. Once the design is converted to a gate level schematic and further placed and routed [ implemented ] into a physical chip.


Gate delays and Interconnect delays may affect the operation at the desired frequency.

Dynamic Timing Analysis



Hence  DTA is the functional verification of the gate level net list [ also called as the BACK ANNOTATED NETLIST ].  DTA requires to generate Test Vectors at the inputs of the design.  These vectors are input at the desired operating frequency. DTA has limitations that  The timing coverage may be Incomplete [ as writing test vectors is the responsibility of test engineer].  DTA requires,  Gate level net list.  Device simulation library with timing information of gates  Back annotation data i.e. Timings of Interconnects.

Techniques for Improving Speed

 

Keep the logic gate depth shallow between flip-flop. Avoid circuit designs that have highly loaded gates in the critical path.  A gate delay will increase as the capacitive load is increased on the output of the gate. Duplicate logic to reduce fanouts.

Conclusion


What we have covered  What is the role of STA in VLSI.  Basics, which will help you in timing analysis of your design. what we have missed  Clock tree designing - ASIC issue.  Role of PLL and DLL in chips. Remember..!  STA is complicated in REAL world.  Don t be in hurry while doing STA of your design.  Use proper and crisp words when STA talk is going on.  Take care of Worst case and Best Case delay Values during Timing Analysis.