Verification Automation using IPXACT

Rohit Jindal & Raman Singla ST Microelectronics

Date 22nd Dec,2011

Agenda
Typical Challenges in verification Using IP-XACT for verification platform integration Using IP-XACT for register test generation IP-XACT history Q&A

Introduction
Ever increasing design complexity
IP Integration Verification

Increased Cost
~80% cost is head-count related

TTM pressures
~89% of designs go over deadline by avg. 44%

DAC Study

significant efforts

Typical challenges in verification

Developing Testbench
Integration of components Configuration of IPs

Developing Register test cases Changes are inevitable during design process
Add/remove registers Register definition/bit fields Register location Register type Register implementation Monotonous work

How to be consistence with Design and Architecture Team

What if we have ?
One specification for all information All representations/code generated from the single source Single description for all registers Fully automated flow Industry (IEEE) standard

What are the solutions ?

Excel based solutions In house solutions CIDL Use IEEE IP-XACT standard
IP-XACT

What is IP-XACT ?
IP-XACT is an XML schema and semantics providing: Unified authoring, exchange and processing of design meta-data Complete API for meta-data exchange and database querying IP-XACT enabled meta-data provides language (and vendor) independent description for IPs Component meta-data describes IP ports and interfaces Registers IP Configurable parameters Design meta-data describes: Component instances Connectivity Provides mechanism to model IP at different abstraction levels

IP-XACT Objects
An IP-XACT description of a design or component consists of a set of XML documents referring to one another: Main document types are:
Component A description of a component type, including interfaces, memory maps, and registers (IP) Bus Definition A description of a bus type. Design A high level description of a design (SoC Netlist)

References between IP-XACT document are by 4 element identifier (vendor, library, name and version; often abbreviated to VLNV).

IP-XACT component descriptions

Main elements of components are:
Bus interface B1 Bus type X Slave
Memory map map1

Bus interface B2
Register R0
Register R1

Bus type Y Master

Component
Signal map

Signals
Physical signal Sig1 Physical signal Sig2 Physical signal Sig3

Signal Map

Bus interfaces, referencing bus definitions to describe the bus type Memory maps, including register descriptions Physical signal descriptions

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IP-XACT component XML Example

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IP-XACT Design File

Main elements of components are:
Bus interface B1 Bus type X Slave
Memory map map1

Bus interface B2
Register R0
Register R1

Bus type Y Master

Component
Signal map

Signals
Physical signal Sig1 Physical signal Sig2 Physical signal Sig3

Signal Map

Bus interfaces, referencing bus definitions to describe the bus type Memory maps, including register descriptions Physical signal descriptions

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IP-XACT Design XML Example

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Pre IP-XACT : Separate design threads

IP Spec SystemC Design Environment Verification TB
CPU CPU

System Profiling and Exploration

IP Spec

Verification Solution
implies difficult design iteration and consistency management

No exchange of system configuration

IP Spec

RTL
CPU

Synthesis Solution
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With IP-XACT: Design iteration simplified

SystemC Design Environment
IP-XACT XML

Your IP IP

CPU

System Profiling and Exploration

RTL Design
CPU I

IP-XACT SoC configuration XML Co-Verification Solution

CPU

Synthesis Solution

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Applying IP-XACT to the verification platform Integration What is Required

IP-XACT descriptions of RTL design and verification components

Testbench comprises of
Component instances (design and verification) Connection between components Configurable Parameters of design and verification components

Output
IP-XACT Design file

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TLM IP verification platform generation flow

IP spec
HOST Test Env

C test

ROUTER

IP-XACT
IP-XACT Tool

IP

IP

DUT

IP Database

IP

TLM skeleton

TLM IP

Tool

Verification Plt

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RTL IP verification platform generation flow

IP spec
HOST Test Env

C test

ROUTER

IP-XACT
IP-XACT Tool
IP Database

IP

IP

sc wrapper
BFMs

IP

RTL

RTL skeleton

RTL IP
Tool Verification Plt

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Registers : Typical scenario

Cost per register type
Specifications ( 0.5 page ) Datasheets Register tests RTL register decoder / netlist TLM models / netlist Register tests ( 30 lines per registers* [1..n] ) Register C header, eSW (20 lines per registers *[1..n]) Memory map representation ( ?? )

There are hundreds of register in a typical IP Who will ensure coherency ?

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Use IP-XACT and auto-generate all register specific codes from this file

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Register Generation Flow

IP spec

IP-XACT
IP-XACT Tool

Register testcases

HOST

Test Env

test

C header/test
IP

ROUTER
IP

DUT

IP

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Design Flow using IP-XACT

Datasheet export
Datasheet

Tech Pub
Header / Reg test export
IP C header IP Register test

IP / (Sub)system architect
Functional Spec

IP -XACT Description

TLM Skeleton / netlist export

Chip integration team SW Driver team

TLM Skeleton/ Netlist

Spec import

Check QA

Edit

Cosim wrapper export

TLM Modeling team

Mixed TLM/RTL testbench IP Register test

IP Verification team Register bank export

Verilog RTL decoder

IP Design Team
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IP-Xact benifits
Standard allows multi vendor IPs/EDA tools use. Simplified integration Coherency with other design teams
No duplication

Automatic flow to avoid manual repetitive jobs Benefits: dramatic TTM Improvements

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How SPIRIT evolves

Six companies started the SPIRIT Consortium in 2003 with the initial goal is to provide a standard for describing IP to enable maximum design automation with multisource IPs/multi vendor design flows reuse vendor neutral approach IP-Xact evolves as an industry standard to describe IPs IP-Xact now an IEEE standard(p1685) SPIRIT Consortium now merge with another EDA PHILIPS standards organization, Accellera
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Background of IP-Xact
IP-XACT 1.5 was handed off to the IEEE P1685 Working Group in late June 2009. Later in June 2010, IEEE released the standards as IEEE Std1685-2009 Merger of Electronic Design Automation (EDA) industry organizations, Accellera and The SPIRIT Consortium

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IP-XACT TC Objectives and Goals

To collect requirements from all members for IP-Xact enhancements Discuss and proposed solution amongst TC members Update IP-Xact standard as accellera extensions Handover the IP-Xact Accellera extensions to IEEE To ease the adoption of IP-Xact standard in industry If you liked IP-XACT based flow and want to participate in TC, join us through Accellera.

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On the lighter side

Present Verification plan and reports are in XML Output logs and debug reports are in XML Near Future Comments of code in XML Minutes of meeting in XML Future Discussion between team members in XML
For no further discussion - slash(/) discussion

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On the lighter side

Future Resume of engineer
<skillset>VHDL,Verilog</skillset>

Interviewer asking candidate what is your VLNV

Grenoble Institute of Technology, Electronics, Gregory Bernard, 2010

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<lastslide> Thanks </lastslide>

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Thanks ! Questions?

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