1.

2 Memory
1.2.1 Memory Organization 1.2.2 Memory Read and Write 1.2.3 Memory Map 1.2.4 Microcomputer System

1.2.1 Memory Organization

Introduction of Memory: Memory is essential part of

microprocessor based system or any microcomputer. It is used to store binary information either instruction or data and it also provide to microprocessor whenever required by microprocessor. Memory can be divided in two basic categories. 1. Primary Memory: It can be accessed directly by microprocessor. Two types of primary memory are RAM and ROM. 2. Secondary (Storage) Memory: It can not be accessed directly by microprocessor. To access content of secondary memory, we have to move that data into primary memory. Secondary memory can also divide in to two parts. Serially access and Semi random access.
2

Memory Organization cont..

RAM memory is group of registers. These registers are arranged in sequence and

always in the power of 2. Each register of memory is made from group of flip-flop or FET (Field effect transistor) which can store one bit information and thats why flip-flop is known as a memory cell. classify RAM Memory according to their memory word size. For example 4-bit memory, 8-bit memory, 16-bit memory etc. In case of 4-bit memory each register of memory can store 4-bit size of data.

Each register stores group of bits, which is known as memory word size. We can

RAM memory is also known as volatile memory because if power supply cut or

off then data stored in memory is lost. We can read as well as write inside the RAM memory.
supply cut or off then data stored in memory remains as it is. We can only read from ROM memory. ROM memory is made from group of diode and group diode can be viewed as register. unique binary combination known as address or memory location.

ROM memory is known as permanent or non-volatile memory because if power

Now, we know memory is group register and we can identify each register by
3

Memory Organization cont..

If microprocessor has to communicate with memory then it

has to perform following three steps: 1. Identify memory chip (using part of the address bus). 2. Select register (using the rest of the address bus). 3. Read or Write from memory (using the data bus and control bus). Microprocessor 8085 can performed first and second steps with the help of address bus and perform third step of read or write from memory with the help of data bus and control signals. Data bus carrying data between microprocessor and memory and control bus provides necessary control signal.
4

Memory Cell and Memory Register: Memory is a circuit used to store binary information, either in the form of voltage or capacitive charge. Flip-flop can store one bit information and thats why it is known as memory cell. D latch flip-flop is used inside memory. Before learning Latch (1 bit memory) or Register (4 or 8 bit memory), we must have bit knowledge about Tri- State Buffer. Tri State Buffers: An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states of output (tri-state means three state): Logic 0, logic 1 and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely. This circuit has two inputs and one output. 1. Data Input: First input behaves like the normal input for the circuit. 2. Control Input : Second input is an enable.
5

Tri State Buffers:

To understand the operation of circuit for active high enable signal (as in fig. a) If Enable is set high, the output follows the proper circuit behavior. If Enable is set low, the output looks like a wire connected to nothing. Likewise to understand the operation of circuit for active low enable signal (as in fig. b) If Enable is set low, the output follows the proper circuit behavior. If Enable is set high, the output looks like a wire connected to nothing.

Memory Cell: Latch or D Flip Flop:

The basic memory element is similar to a D flip flop or latch. This latch has an input where the data comes in. It has an enable input and an output on which data comes out. In case of D latch flip-flop if enable signal is active then what ever at the input line that binary value stored inside the flipflop and always stored value is available at the output. But, the basic D latch flip-flop has two limitations. 1. Unintentional change in the input of D latch flip-flop affects the stored value. 2. Stored value of D latch flip-flop is always available at the output.

Latch or D Flip Flop: cont

Solution: Above mentioned 02 limitations can be removed by adding two tri-state buffers; one is at the input line and second is at the output line. We connect WR control signal to the enable of input tri-state buffer and connect RD control signal to the enable of output tri-state buffer.

The Basic Memory Element (D Latch) has following 02 signals: 1. The WR signal controls the input buffer. The bar over WR means that this is an active low signal. So, if WR is 0 the input data reaches the latch input. If WR is 1 the input of the latch looks like a wire connected to nothing. 2. The RD signal controls the output in a similar manner. The bar over RD means that this is an active low signal. So, if RD is 0 the stored data of latch reaches to the data output. If RD is 1 the stored of the latch looks like a wire connected to nothing. Now, if we want to store any value inside the D latch flip-flop then we have to give that value at input line then make WR control signal active or low. Like wise if we want to read stored value of D latch flip-flop then we have to make RD control signal active or low. Thus, we removed two limitations of basic D latch flip-flop that unintentional change in input will affect the store value and not control on the availability of output.
9

Memory Register:
Now, if we want to design four bit register then we have to

use four D latch flip flops. Short the enable signal of all four flip-flops and it becomes master enable signal, like wise short the enable of all input tri-state buffer of all four flip-flops and it connected WR control signal, like wise short the enable of all output tri-state buffer of all four flip-flops and it connected RD control signal. There are four input and output lines of 4-bit register, as there are four D latch flip-flops used.

10

Group of Memory Registers:

If we combine four 4-bit register then it referred as 4 X 4 Memory chip. In the notation first digit indicates numbers of register in a memory chip or different memory word and second digit indicates memory word size or numbers of bit stored by each register or memory.
The capacity memory is 4 x 4 = 16 bits or four nibble. Group of four bits is known as nibble and group of eight bits is known as byte. So, we can specify the capacity or size of memory in Kbytes or bytes or bits.

To convert bytes into Kbytes, we have to divide numbers of bytes by 1024. Because, in the case of any programmable machine 1024 bytes = 1KB
11

Design of a Memory Chip:

Using the RD and WR controls, we can determine the direction of

flow either into or out of memory. Then using the appropriate Enable input we enable an individual memory register. What we have just designed is a memory with 4 locations and each location has 4 elements (bits). This memory would be called 4 X 4 [Number of register or location X number of bits per location].

Produce Enable Input line: As we know that we can never have more than one of these enables active at the same time. So we can have them encoded, to reduce the number of lines coming into the chip. These encoded lines are the address lines for memory. So, the previous diagram would now look like the following:
12

Design of a Memory Chip:

13

Design of a Memory Chip:

As we have tri-state buffers on both the inputs and outputs of the flip flops, so we can actually use only one set of pins for both input and output. The chip would now look like this:

14

Expansion of Memory:
Whenever we want to increase the size or capacity of memory then

we expands the memory. Thus, by expanding the memory, we increase the size or capacity of memory. We can expand memory by two technique and they are as followings: 1. Series connection: If we connect two or more memory chip in series then in the expanded memory, numbers of register are going to increase which increases the numbers of address lines. 2. Parallel connection: If we connect two or more memory chip in parallel then in the expanded memory, the memory word size is going to increase which increases the numbers of data lines.
If we have free address lines in microprocessor and we have to

increases numbers of register then connect two or more memory chip in series. Similarly, if we have free data lines in microprocessor or we have to increases numbers of memory word size then connect two or more memory chip in parallel.
15

1.2.2 Memory Read and Memory Write:

Microprocessor performs two types of communication with memory that

is memory read and memory write. To do any one communicate with memory, microprocessor has to perform three steps.
Memory Read Operation: It has three steps as follows:

Microprocessor identify memory chip by enabling or activating the CS (Chip Select) signal of memory chip by keeping appropriate logic level on the address line connected to the chip select interfacing logic . 2. Microprocessor select the memory register by putting appropriate logic level on the address line directly connected to memory chip which known as Register Select line. 3. Microprocessor generates memory read (MEMR) control signal which connected to RD control signal of memory chip. As soon as memory read control signal becomes active the content of selected register placed on the data bus and from data bus it goes inside microprocessor.
1.
16

Memory Read and Memory Write:

Memory Write Operation: it has three steps as follows: 1. It identify memory chip by enabling or activating the CS

(Chip Select) signal of memory chip by keeping appropriate logic level on the address line connected to the chip select interfacing logic . 2. It select the memory register by putting appropriate logic level on the address line directly connected to memory chip which known as Register Select line. 3. It generates memory write (MEMW) control signal which connected to WR control signal of memory chip. As soon as memory write control signal becomes active the data placed by microprocessor on the data bus goes inside selected register.
17

Memory Read and Memory Write:

Differences between memory read and memory write

operations.
Memory Read Operation 1 2 Memory Write Operation

Memory read control signal Memory write control signal activates. activates . Data flow occurs from Data flow occurs from memory to microprocessor microprocessor to memory First control signal memory read generates and then data of selected memory register placed on the data bus. First data from microprocessor placed on the data bus and then control signal memory write generates.

18

Address Decoding Technique:

There are two types of address decoding techniques as follows:
1.

Complete or Absolute address decoding technique: If all the address lines of microprocessor used for interfacing with memory than it known as complete address decoding technique. In this method each register of memory will get unique or absolute address and thats why it is also known as absolute address decoding technique. This address decoding technique required more hardware. So, the cost is going to increase. Partial or Duplicate address decoding technique: If few of the address lines of microprocessor used for interfacing with memory than it known as partial address decoding technique. In this method each register of memory will get more than one address and thats why it is also known as duplicate address decoding technique. This address decoding technique required less hardware. So, the cost is going to decrease.

2.

19

1.2.3 Memory Map:

In 8-bit microprocessor the address bus is of 16 address lines and it

used 16-bits address to identify the register of memory chip. Thus, it is known as 16-bits address scheme. Now, we know group of four bits equal to one hexa digit. So, 16-bits represent 04 hexa digits. Thus, in the case of microprocessor 8085, the address range is 0000 H to FFFF H which is 64 Kbytes. We can define memory mapping is the pictorial representation in which different memory devices allocated to the entire range of memory address. So, from memory map, we can locate different memory device of the system. We can also change the address range of memory chip by changing the logic of interfacing device.
Memory Map and Addresses Range: The memory map is a pictorial

representation of the address range and shows where the different memory chips are located within the address range.
20

Memory Map:

21

Designing of memory model for microprocessor 8085 based system :

The following steps must be kept in mind while designing memory model for

1.

2.

3.

4.

microprocessor 8085 based system. A memory chip requires address lines to identify a memory register. The number of address lines required is determined by the number of registers in a chip (2n = Number of register, where n is the number of address lines). The 8085 microprocessor has 16 address lines. So, out of 16 address lines, the address lines necessary for the microprocessor chip must be connected to the memory chip. A memory chip requires a chip select (CS) signal to enable the chip. The remaining address lines (from step 1) of the microprocessor can be connected to the chip select (CS) signal through an interfacing logic. The address lines connected to CS, select the chip. Similarly the address lines connected to the memory chip, select the register. Thus, the memory address of a register is determined by the logic levels (0/1) of all the address lines (including the address lines used for CS) The control signal RD enables the output buffer and data from the selected register are made available on the output lines. Similarly, the control signal WR enables the input buffer, and data on the input lines are written into memory cells. The microprocessor can use its memory read and memory write control signals to enable the buffers and the data bus to transport the contents of the selected register between the microprocessor and memory.

22

Dimensions of Memory:
Memory is usually measured by two numbers: length and width (Length X

Width). 1. The length is the total number of locations or registers. The length (total number of locations or registers) is a function of the number of address lines. Number of memory locations = 2address lines So, a memory chip with 10 address lines would have 210 = 1024 locations (1K) Looking at it from the other side, a memory chip with 4K locations would need Log2 4096=12 address lines 2. The width is the number of bits in each location or register.

The 8085 and Memory: The 8085 has 16 address lines. That means it can address 216 = 64K memory locations. Then it will need 1 memory chip with 64 K locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc.

23

Cont..
How would we use these address lines to control the multiple chips? Chip Select Usually, each memory chip has a CS (Chip Select) input. The chip will only work if an active signal is applied on that input. To allow the use of multiple chips in the make up of memory, we need to use a number of the address lines for the purpose of chip selection. These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used. Chip Selection Example Assume that we need to build a memory system made up of 4 of the 4 X 4 memory chips we designed earlier. We will need to use 2 inputs and a decoder to identify which chip will be used at what time. The resulting design would now look like the one on the following slide.
24

Design of a Memory Chip: Revisited

25

Chip Select Example:

26

Address range of a Memory Chip:

The address range of a particular chip is the list of all addresses that are mapped

to the chip. An example for the address range and its relationship to the memory chips would be the Post Office Boxes in the post office. Each box has its unique number that is assigned sequentially. (memory locations) The boxes are grouped into groups. (memory chips) The first box in a group has the number immediately after the last box in the previous group. The above example can be modified slightly to make it closer to our discussion on memory. Lets say that this post office has only 1000 boxes. Lets also say that these are grouped into 10 groups of 100 boxes each. Boxes 0000 to 0099 are in group 0, boxes 0100 to 0199 are in group 1 and so on. We can look at the box number as if it is made up of two pieces: The group number and the boxs index within the group. So, box number 436 is the 36th box in the 4th group. The upper digit (4) of the box number identifies the group and the lower two digits (36) identify the box within the group.
27

The 8085 and Address Range:

The 8085 has 16 address lines. So, it can address a total of 64K

memory locations. If we use memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip needs 10 address lines to uniquely identify the 1K locations. (log21024 = 10) That leaves 6 address lines which is the exact number needed for selecting between the 64 different chips (log264 = 6).
Now, we can break up the 16-bit address of the 8085 into two

pieces: A15 A14 A13 A12 A11 A10

A9 A8 A 7 A6 A5 A4 A3 A 2 A1 A0

Depending on the combination on the address lines A15 - A10 , the

address range of the specified chip is determined.

28

Chip Select Example:

A chip that uses the combination A15 -

A10 = 001000 would have addresses that range from 2000H to 23FFH.
Keep in mind that the 10 address lines

on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips.
The memory chip in this example would

require the following circuit on its chip select input:

Now the chip would have addresses

ranging from: 2400 to 27FF.

Changing the combination of the address

bits connected to the chip select changes the address range for the memory chip.
29

To illustrate this with a picture:

In the first case, the memory chip occupies the piece of the

memory map identified as before. In the second case, it occupies the piece identified as after.
30

High-Order vs. Low-Order Address Lines:

The address lines from a microprocessor can be classified into two types: 1. High-Order: Used for memory chip selection 2. Low-Order: Used for location selection within a memory chip. This classification is highly dependent on the memory system design.

Data Lines All of the above discussion has been regarding memory length. Lets look at memory width. We said that the width is the number of bits in each memory word. We have been assuming so far that our memory chips have the right width. What if they dont? It is very common to find memory chips that have only 4 bits per location. How would you design a byte wide memory system using these chips? We use two chips for the same address range. One chip will supply 4 of the data bits per address and the other chip supply the other 4 data bits for the same address.
31

32

1.2.4: Microcomputer System:

The 8085 MPU module includes devices such as the 1. 8085 Microprocessor 2. An octal latch to de-multiplex low order address bus using signal

ALE (Address Latch Enable) from multiplexed low order address / data bus 3. Logic gate to generate necessary control signals. (04 active low control signals: MEMR, MEMW, IOR and IOW. ) Thus, the figure of microcomputer system shows the de-multiplex address bus, the data bus and four active low control signals. In addition to increase the driving capacity of the buses 1. A unidirectional bus driver is used for the address bus 2. A bidirectional bus driver is used for data bus The chip select decoder decodes the constant logic of address line connected to it and generate chip select signal which select the chip. The remaining address lines connected directly to the address line of memory chip which select the register.

33

Microcomputer System:

cont

In RAM memory we connected both the control signals MEMR and MEMW, where in the case of ROM memory we connected only one control signal MEMR. The port select decoder decodes the constant logic of address lines connected to it and it generates I/O address pulse. The I/O address pulse combine with IOR control signal by two input AND gate in the case of input device to generate I/O select pulse. The I/O address pulse combine with IOW control signal by two input AND gate in the case of output device to generate I/O select pulse. The I/O select pulse connects to enable signal of buffer in the case of input device and enable signal of latch in the case of output device. The data bus connected to all the peripheral including memory.
34

Example of Microcomputer System:

35

Output Selection of the Microcomputer System:

High Order Address Addres Bus Low Driver Bus Order Address s Bus Bus 8085 MPU MEMR MEMW IOR IOW Port Select Decoder

AND Gate
EN Latch

LED

Bus Driver Bidirec tional

36

Data Bus

Thanks

For any Query Contact: Gaurav P. Dave E-mail : gaurav.dave@nirmauni.ac.in