I/O Processors and I/O channels

Presented By: Sudhir Bagul ME-1101008

Obtaining maximum concurrency in I/O Processing :

The logical solution to the problem of obtaining maximum concurrency in I/O processing is to deploy an Intelligent I/O system , which isolates the CPU from the I/O peripheral. It frees the CPU to proceed at a full speed with its primary task of internal program processing.

What is an Intelligent I/O subsystem :

Facilitated by an I/O processor (IPO)

Intelligent I/O subsystem Architecture

As shown in given figure, I/O processor is attached directly to the system bus It is responsible for selecting and retrieving individual I/O commands from main memory. IPO contains the processor specifically designed for I/O processing and a number of I/O channels. When exists alone a channel may be a small processor that performs DMA operations for a small set of devices. When the channel is incorporated within a IOP it is essentially a passive component with no logical processing.

Channel Architecture :
There are two types of channels 1> Selector 2> Multiplexer as used in the IBM 370 system.

Selector Channel Architecture :

Selector channel is an IOP designed to handle one I/O transaction at a time. The selector channel is used normally to control high-speed I/O devices such as fixed-head disks and drums. The channel consists of word assembly and disassembly registers. Known as WAR and WDR. Channel can receive and transmit the data in character, halfword, or fullword mode. Overrun error or buffer full interrupt can be solved by double buffering the input data.

The initialization of the selector requires the definition of the location of the first word in memory, the length of the block to be transferred, and the device address. The registers used in this case are the : DAR: device address register BCR: block count register MAR: memory address register CAW: channel address word

The word which was stored prior to initiation of the I/O transaction, contains the starting address of the I/O program to be executed by the channel. This program is called as channel program the channel program consists of channel command word (CCW) or controls words, or instructions. The typical maximum data rate of selector channel is on the order of 1 to 3 megabytes

Character-Multiplexor Channel Architecture :

The multiplexor channel is an IOP which can control several different transactions concurrently. The data transfers are time multiplexed over the I/O interface. This channel type is divided into Block multiplexor character multiplexor

Character multiplexors are used to handle low-speed devices. Block multiplexors are used to handle medium-speed devices. The block/character multiplexor consists of the set of subchannels, each of which can act as a low-speed selector channel. Subchannel contains a buffer, device address register, request flag, and some control and status flags. The subchannels share global channel control.

The intel-8089 I/O processor with two separate I/O channels :

With the current technology an I/O processor can be implemented on a single chip of microcomputer and minicomputer systems. Example of an IOP on a chip is the INTEL 8089 integrated IOP, which is capable of being interfaced to 8-bit and 16-bit systems. This IOP contains two independent I/O channels and a processor on the same chip.

The intel-8089 I/O processor with two separate I/O channels :

It contains a bus interface, an assemblydisassembly register file and instruction fetch unit. To enable autonomous operations of the I/O channels, each channel maintains its own register set, control and status registers, and a flexible channel controller The bus control and interface logic are shared by the two channels. The IOP is capable of alternating between the two channels with every internal cycle (4 to 8 clock).

Register set of a channel in Intel IOP:

Register set of a channel in Intel IOP:

Each register set of a channel contains eight userprogrammable registers. Four of which are 21-bit-wide address registers, and four registers are 16 bits wide. The address registers can be used to address 1 megabyte of system memory or 64K bytes of I/O space. Bit 20 of the address register is used to select the address space as system or local I/O space. The GA and GB registers are used to reference the source and destination location.

The GC register is used as general register pointer by channel program. The task pointer (TP) serves as the channel program counter, which is initialized whenever the channel is started. Using the TP, the instruction unit in the IOP can fetch the next CCW. The TP can also be manipulated by the channel program. The byte register (BC) contains the number of bytes to be transferred during DMA operations. The index register (IX) is used as an index in the indexed addressing mode.

Simplified computational model of the Intel I/O processor :

Simplified computational model of the Intel I/O processor :

After reset, a channel attenstion (CA) input pulse forces an internal initialization sequence. Then the processor is ready dispatch an I/O transaction request to either of the two channels to perform the desired I/O task. The I/O channel begins its operation in the task block (TB) state with the execution of the I/O program and enters the DMA state under IOP program control.

In this state the channel proceeds with the high-speed data transfer in either burst or request-synchronization mode until the occurrence of a valid termination condition, which returns the channel to the TB state. HALT commands force the channel into the idle state until further dispatching occurs.

Logical representation of peripheral processing subsystem :

For CDC-6600 and Cyber-170

In the CDC 6600 and Cyber 170 I/O subsystem, integrated IOP is used as the peripheral processing subsystem (PPS). It consists of a set of 10 peripheral processing units (PPU) which shares a set of channel to which devices and their controllers are connected. The CDC 6600 integrated peripheral processor uses a barrel design to share logical units within the IOP. It uses a set of registers to share a common arithmetic logic unit and a data distribution system in a synchronous fashion.

Barrel processing of I/O transaction in CDC :

The barrel contains 10 peripheral processing units (PPUs) and a PPU is 12-bits wide. A PPU instruction requires a number of steps for its execution. The execution in each step is performed in a distinct slot which logically represents a PPU. PPU instruction is executed as in cyclic pipeline process. Each instruction cycle is an integral number (up to 10) of minor cycles.

A minor cycle is 100 ns and a major cycle is 1000 ns, hence the 10 PPUs are used. PPU operates once per major cycle, the maximum data rate is

12 bits / 1000 ns = 12 * 10^6 bits/s.

Therefore 10 PPUs are time shared by the slot hardware without significant degradation in performance. Since the CDC 6600 is a 60-bit computer, five PPU transfers are required to form a 60-bit word.

I/O configuration in system with cache :

I/O configuration is system with cache:

In the first configuration the I/O channel can be attached to the cache so that the cache is shared by the processor and channel. The channel competes with the processor for access to the cache. An I/O channel is often slower than the processor. Thus connecting the channel to the cache does not improve the performance of I/O transfer.

This increase is caused by three main effects : Main memory update of memory-bound I/O data. Misses caused by channel fetches from memory. Channel programs (and I/O data) occupying cache, reducing the effectives cache aggregate miss ratios seen by processor-bound jobs.

The alternate configuration is to connect the channel to the memory directly. In this case the channel competes with the cache controller for access to the memory. The I/O channel and processor executions conflicts at miss time only, assuming a write back update policy. One major drawback: data consistency or coherence problem.

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