Atmega16 Interrupts

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4/11/12

Interrupts
n n

Atmega16 has 3 external interrupts and 17 internal interrupts These interrupts and the separate reset vector each have a separate program vector in the program memory space All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors The complete list of vectors is shown in a table on next slide

More Details on Page 11 and Page 42 of Datasheet 4/11/12

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Interrupt
When an interrupt occurs, the Global Interrupt Enable Ibit is cleared and all interrupts are disabled n The I-bit is automatically set when a Return from Interrupt instruction is executed n The interrupts have priority in accordance with their interrupt vector position n The lower the interrupt vector address, the higher the priority What does it mean? n Like 8051 you cannot set the interrupt priority in Atmega16 the only solution is nested interrupt (interrupt with in an interrupt)
n

More Details on Page 11 and Page 42 of Datasheet 4/11/12

Nested Interrupts
n

The user software can write logic one to the I-bit to enable nested interrupts All enabled interrupts can then interrupt the current interrupt routine

More Details on Page 11 and Page 42 of Datasheet 4/11/12

External Interrupts
External Interrupt n The External Interrupts are triggered by the INT0, INT1, and INT2 pins Internal Through External Interrupt n If enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs n This provides a way of software interrupt INT0 and INT1 n The external interrupts can be triggered by a falling or rising edge or a low level INT2 n It is only edge triggered
More Details on Page 64 of Datasheet 4/11/12

Registers Associated with Interrupts

Following are the registers which contains different bits that control the interrupts n Status Register (SREG)
q q

Bit-I (7) of SREG is Global Interrupt Enable bit This bit must be set for the interrupts to be enabled

More Details on Page 7 of Datasheet 4/11/12

Registers Associated with Interrupts

n

General Interrupt Control Register GICR

Bit 7 INT1: External Interrupt Request 1 Enable

n

When the INT1 bit is set (one) the external pin interrupt 1 is enabled The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt Vector

More Details on Page 65 of Datasheet 4/11/12

External Interrupts Resgisters

n

Bit 6 INT0: External Interrupt Request 0 Enable

q

When the INT0 bit is set (one) the external pin interrupt 0 is enabled The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt Vector

Bit 5 INT2: External Interrupt Request 2 Enable

q

When the INT2 bit is set (one) the external pin interrupt 2 is enabled The corresponding interrupt of External Interrupt Request 2 is executed from the INT2 interrupt Vector

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External Interrupts Resgisters

n

Last four bits of this register controls the mode of external interrupt 0 and 1

MCU Control Register (MCUCR)

Bit 3, 2 ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 (Interrupt 1 Sense control)

4/11/12 More Details on Page 64 of Datasheet

External Interrupts Resgisters

q

Bit 1, 0 ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 (Interrupt 0 sense control)

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External Interrupts Resgisters

n

MCU Control and Status Register MCUCSR

q

Bit-6 of this register controls the mode of interrupt 2

If ISC2 is written to zero, a falling edge on INT2 activates the interrupt If ISC2 is written to one, a rising edge on INT2 activates the interrupt

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External Interrupts Resgisters

n

For Interrupt 0
q q q

Set the SREG bit-I Set the INT0 pin of GICR Select its mode by setting bits ICS01 and ICS00 of MCUCR accordingly Set the SREG bit-I Set the INT1 pin of GICR Select its mode by setting bits ICS11 and ICS10 of MCUCR accordingly

For Interrupt 1
q q q

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External Interrupts Resgisters

n

For Interrupt 0
q q q

Set the SREG bit-I Set the INT2 pin of GICR Select its mode by setting bit ISC2 of MCUCSR accordingly

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External Interrupts Flags Register

n

General Interrupt Flag Register GIFR

Bit 7 INTF1: External Interrupt Flag 1

n n n

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one) The flag is cleared when the interrupt routine is executed If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector Alternatively, the flag can be cleared by writing a logical one to it This flag is always cleared when INT1 is configured as a level interrupt

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External Interrupts Flags Register

q

Bit 6 INTF0: External Interrupt Flag 0

n n n

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one) The flag is cleared when the interrupt routine is executed If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector Alternatively, the flag can be cleared by writing a logical one to it This flag is always cleared when INT0 is configured as a level interrupt

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External Interrupts Flags Register

q

Bit 5 INTF2: External Interrupt Flag 2

n n n

When an edge or logic change on the INT2 pin triggers an interrupt request, INTF2 becomes set (one) The flag is cleared when the interrupt routine is executed If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector Alternatively, the flag can be cleared by writing a logical one to it

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Example
#include <avr/io.h> #include <avr/interrupt.h> unsigned char z=0; void main() { DDRB=0xFF; //Configures port B as output DDRD|=0b00001000; //configure bit4 of port D as intput SREG=SREG|0b10000000; //Enabling Global Interrupt GICR=0b10000000; //Enabling Interrupt 1 MCUCR=(1<<ISC10|0<<ISC11); //selecting mode of interrupt 1 while(1) { PORTB=z; //continuously outputs z } } ISR(INT1_vect) { z++; }4/11/12

Vector Names for WinAVR(AVR GCC)

External interrupt 0 External interrupt 1 External interrupt 2 ADC Conversion Complete Analog Comparator Serial Transfer Complete Store Program Memory Ready Timer/Counter0 Compare Match Timer/Counter0 Overflow Timer/Counter Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare MatchB Timer/Counter1 Overflow INT0_vect INT1_vect INT2_vect ADC_vect ANA_COMP_vect SPI_STC_vect SPM_RDY_vect TIMER0_COMP_vect TIMER0_OVF_vect TIMER1_CAPT_vect TIMER1_COMPA_vect TIMER1_COMPB_vect TIMER1_OVF_vect

Complete table available at : 4/11/12 http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html